****** PlanAhead v13.4 (64-bit)
  **** Build 157570 by hdbuild on Fri Dec 16 13:06:31 MST 2011
    ** Copyright 1986-1999, 2001-2011 Xilinx, Inc. All Rights Reserved.

INFO: [Common-78] Attempting to get a license: PlanAhead
INFO: [Common-82] Got a license: PlanAhead
INFO: [Common-86] Your PlanAhead license expires in -563 day(s)
INFO: [Device-25] Loading parts and site information from C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts\arch.xmlParsing RTL primitives file [C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
Finished parsing RTL primitives file [C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts\xilinx\rtl\prims\rtl_prims.xml]
source C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/planAheadScript.tcl
# create_project -part xc5vlx30ff676-1 toplevel_gen C:/NIFPGA/jobs/G2K2D0O_KSw9nkc
# add_files C:/NIFPGA/jobs/G2K2D0O_KSw9nkc
# set_property top toplevel_gen [get_property srcset [current_run]]
# open_rtl_design
Design is defaulting to part: xc5vlx30ff676-1
INFO: [PlanAhead-58] Using Verific elaboration
Parsing VHDL file "C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
Parsing VHDL file "C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts\xilinx\rtl\lib\synplify\synattr.vhd" into library synplify
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiUtilities.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgFxp.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgFxpArithmetic.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpShiftCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgFloat.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpEnableHandlerSlv.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDynamicShift.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgGray.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\PkgCcConstants.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\PkgBeatleSettings.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpEnableHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatToFixedCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpNormalize.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpAddSub.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopSLV.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\PkgRegs.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiLvPrims.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\PkgGlobalConst.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgFxpDivide.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'PkgCartridge.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCartridge.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCartridge.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'PkgBeatleTypedefs.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgBeatleTypedefs.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgBeatleTypedefs.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpCoerce.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatToFixed.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFixedToFloat.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivRnd.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivPreproc.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivInt.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopUnsigned.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopGray.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopBoolVec.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SyncFifoFlags.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PulseSyncBase.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrioInterface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCommIntConfiguration.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'PkgCcParameters.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCcParameters.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCcParameters.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\PkgCcHsiSettings.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvToInteger.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvToFloatingPoint.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvToFixedPoint.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaRegisterCoreBase.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaDualPortRam_Inferred.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\GenDataValid.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivSigned.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncAsyncInBase.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopSlvResetVal.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcSpiDither.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcBarrelShifter.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PulseSyncBool.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaUtilities.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaFifoGenericValue.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaCoresFifo.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrioCommInt.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9220.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCommunicationInterface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpMultiCycleEnableHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatMultiplyCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatDivideCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvCoerce.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaRegisterCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaPulseSyncBaseWrapper.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoFlags.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaDualPortRam.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\HandshakeBase.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncBase.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopFallingEdge.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcSpiDitherHardcodable.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcSourceSynchFalling.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcSourceSynch.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcMuxSL4.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcMuxSL3.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcMuxSL2.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'CcHsOutputLogic.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsOutputLogic.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsOutputLogic.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'CcHsInputLogic.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsInputLogic.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsInputLogic.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaFifo.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaBoolOp.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrioCiHsiEngine.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrioCal.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9403IoNode.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9264Cal.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9220Cal.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9213.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9205.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpMultiply.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpDivide.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatMultiply.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatDivide.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatCompareCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFlipFlopFifo.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoPortReset.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifo.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\HandshakeBool.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoWriteAdapter.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoReadAdapter.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FeedbackNonSctlCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncBool.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DmaMiteWriteRegs.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DmaMiteReadRegs.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DmaDisabler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopBoolFallingEdge.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopBool.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioParallelCrcCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiSpiConfig.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiPinConfig.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiModeSelectorControl.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CpuDataWr.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CpuDataRd.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'CcSpiLogic.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcSpiLogic.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcSpiLogic.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'CcMuxSLN.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcMuxSLN.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcMuxSLN.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

Parsing VHDL file ".\.Xil-PlanAhead-5044-\xlicmgr\CcInputFlop.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'CcHsOutput.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsOutput.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsOutput.vhd" into library work
Release 13.4 - Xilinx License Manager (xlicmgr) O.87xd (nt64)

Copyright (c) 1995-2011 Xilinx, Inc.  All rights reserved.

ERROR:coreutil - ios failure

ERROR:sim:928 - Could not open destination 'CcHsInput.vhd' for writing.

WARNING: [Netlist-8] Can not read encrypted file 'C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsInput.vhd' because xlicmgr command failed; please check the xlicmgr messages at the terminalParsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsInput.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\TimeoutManager.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ResetSync.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PulseSyncSL.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9264.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9213Cal.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9211Cal.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9211.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9205Cal.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvMultiply.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpCompare.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatCompare.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvDivide.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaSimpleModuloCounter.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaSimpleCounter.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaShiftReg.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaMiteWriteInterface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaMiteReadInterface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaMergeErrors.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaLocalResHolderWrite.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoPopBuffer.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoClearControl.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaBoolOp.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\HandshakeSLV.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FloatingFeedbackGInit.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncSL.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStockSpiEngine.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStockModuleId.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStockModeSelector.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStockEepromRead.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioSourceSync.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioEepromRead.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiSpiEngine.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiPulseMask.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiPicoBeatleInit.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiOutputMuxes.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiModeSelector.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiInputFlops.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiInitSequence.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiHsiEngine.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiEeprom.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiCrcCheck.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiCartridgeIdentification.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiCartridgeDetection.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403SpiWord.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403LdHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403DoIoNode.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403DioHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403DiIoNode.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9264IoNode.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264CalReciprocal.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223IoNodeResHolder.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220GetCalConst.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213IoNode.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211IoNode.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205_io.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205GenScanLine.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_202.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_189.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_185.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_173.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_132.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arraycollect_232.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arraycollect_187.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arraycollect_175.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arraycollect_136.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\RegisterAccess32.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaIrqRegisters.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9223Shared.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvCompare.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaLoopTimer.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoCountControl.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaBoolOpNot.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e9_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e2_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000c8_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000c4_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000c0_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000bc_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000b8_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000b4_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000b0_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000ac_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000092_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000082_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005d_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002d_CaseStructure_64.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000021_CaseStructureFrame_0001.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000021_CaseStructureFrame_0000.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000013_CaseStructureFrame_0001.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000013_CaseStructureFrame_0000.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaOutput.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaInput.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaComponentEnableChain.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\HandshakeBaseResetCross.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\forloop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\EnableChainSM.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncSlAsyncIn.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStock.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCommInt.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioCalParallelCrc.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioCalMultiply.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioCalMemory.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403EnableChainHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403CommHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264UpdateHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264IoHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264GetCalConst.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264EnableChainHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264CalData.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223SampleValidDelay.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223SampleSerializer.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223IoHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223HseioReadHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223ErrorDecode.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223EnableChainHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223ClockCrossing.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220SampleCounter.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220Initializer.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220CalData.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213UpdateHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213IoHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213GetCalConst.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213FxpScaleData.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213EnableChainHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211IoHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211GetCalConst.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211EnableChainHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211CalData.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9208IoHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205SetTriggers.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205SettingRegs.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205IoHandler.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205GetCalConst.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205ControlSm.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205CommSm.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205CalData.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ArrayIndexNode_27.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ArrayIndexNode_246.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Adapter16.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SubVICtlOrIndOpt.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SubVICtlOrInd.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\resholder_w_opt.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\resholder_r_opt.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\RegisterAccess.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaLocalResHolderRead.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbPowerOf2.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e1_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000df_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000008f_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005c_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005a_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000032_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002e_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000020_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000012_ForLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteWriteInterface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteReadInterface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteIrq.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteInterfaceOutputEnables.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaComponent.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncBoolAsyncIn.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\whileloop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\subMinArray_vi.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\subMaxArray_vi_colon_Clone0.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SafeBusCrossing.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgRegister.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaViControlRegister.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaArbiter.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaRegFrameworkShiftReg.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaHostAccessibleRegister.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbSerializeAccess.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbDelayer.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000fb_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000de_WhileLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000008e_WhileLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000059_WhileLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000004b_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000042_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000001_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteInterface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403ResourceCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9264ResourceCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220SyncResourceLogic.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220ResourceCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213ResourceCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211ResourceCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9205ResourceCore.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ViSignature.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ViControl.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\TopEnablePassThru.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Sleep.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaCtrlIndRegister.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaClockManagerControl.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000010d_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000058_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000000_WhileLoop.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\InvisibleResholder.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\IDSel_Timer.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DiagramReset.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForTopEnablesPortOnResTopEnablePassThru.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForTmax_ctl_5RHFpgaReadPortOnResbushold.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForMiteIoLikePortOnResInterface.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbFordinPortOnResSleep.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForAnsteuerung_beenden_ctl_0RHFpgaReadPortOnResbushold.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403SyncResource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403Resource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9264SyncResource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9264Resource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220SyncResource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220Resource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213SyncResource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213Resource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211SyncResource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211Resource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205_SyncRes.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205_Resource.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio80MhzClkRes.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\bushold.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaStockDcm.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_Speichern4_dash_2FPGA.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\TheWindow.vhd" into library work
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\toplevel_gen.vhd" into library work
CRITICAL WARNING: [EDIF-96] Could not resolve non-primitive black box cell 'NiLvXipFloat32Multiply' defined in file 'NiLvFloatMultiplyCore.vhd' instantiated as 'GenFloat32Multiply.XilinxFloat32Multiply'.
CRITICAL WARNING: [EDIF-96] Could not resolve non-primitive black box cell 'NiLvXipFloat32Divide' defined in file 'NiLvFloatDivideCore.vhd' instantiated as 'GenFloat32Divide.XilinxFloat32Divide'.
CRITICAL WARNING: [EDIF-96] Could not resolve non-primitive black box cell 'InvisibleResholder(2,1)' defined in file 'InvisibleResholder.vhd' instantiated as 'n_InvisibleResholder'.
INFO: [PlanAhead-430] Reading macro library C:/NIFPGA/programs/Xilinx13_4/PlanAhead\./parts/xilinx/virtex5/virtex5lx/hd_int_macros.edn
Parsing EDIF File [C:/NIFPGA/programs/Xilinx13_4/PlanAhead\./parts/xilinx/virtex5/virtex5lx/hd_int_macros.edn]
Finished Parsing EDIF File [C:/NIFPGA/programs/Xilinx13_4/PlanAhead\./parts/xilinx/virtex5/virtex5lx/hd_int_macros.edn]
INFO: [Device-21] Reading bus macro file C:/NIFPGA/programs/Xilinx13_4/PlanAhead\./parts/xilinx/virtex5/pr_bus_macros.xmlLoading clock regions from C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts/xilinx/virtex5/virtex5lx/xc5vlx30/ClockRegion.xml
Loading clock buffers from C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts/xilinx/virtex5/virtex5lx/xc5vlx30/ClockBuffers.xml
Loading package from C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts/xilinx/virtex5/virtex5lx/xc5vlx30/ff676/Package.xml
Loading io standards from C:/NIFPGA/programs/Xilinx13_4/PlanAhead\./parts/xilinx/virtex5/IOStandards.xml
INFO: [Device-19] Loading pkg sso from C:/NIFPGA/programs/Xilinx13_4/PlanAhead\parts/xilinx/virtex5/virtex5lx/xc5vlx30/ff676/SSORules.xml
Loading list of drcs for the architecture : C:/NIFPGA/programs/Xilinx13_4/PlanAhead\./parts/xilinx/virtex5/drc.xml
INFO: [PlanAhead-566] Unisim Transformation Summary:
No Unisim elements were transformed.open_rtl_design: Time (s): 60.394w.  Memory (MB): 564.551p 503.594g
# report_resources -file toplevel_gen_planAheadResults.xml -format xml
INFO: [Designutils-301] Performing resource estimation on toplevel_gen targeting virtex5...
INFO: [Designutils-286] Found 19317 primitives in netlist
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkOut.SyncIReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkOut.SyncOReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkOut.SyncOReset/c2ResetLcl.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncIReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncOReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncOReset/c2ResetLcl.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.oPushToggle1.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkRdy.iRdyPushToggle.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkRdy.iReset.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.oPushToggle1.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkRdy.iRdyPushToggle.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkRdy.iReset.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/BlkOut.SyncIReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/BlkOut.SyncOReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/BlkOut.SyncOReset/c2ResetLcl.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqNum/BlkOut.SyncIReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqNum/BlkOut.SyncOReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqNum/BlkOut.SyncOReset/c2ResetLcl.  Adding 1 LUTs and 2 Flops to estimation.
WARNING: [Designutils-308] Using distributed memory since read port window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/cRioCalMemoryx/cCalMemData is asynchronous.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiCartridgeDetectionx/cCartDetOverrideDone.  Adding 0 LUTs and 1 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiSpiEnginex/SpiEnabled.CcSpiLogicx/oIgnoreFallingEdgeStrobeDelayed.  Adding 1 LUTs and 2 Flops to estimation.
WARNING: [Designutils-308] Using distributed memory since read port window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRio9264CalData/cList is asynchronous.
WARNING: [Designutils-308] Using distributed memory since read port window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioCalMemory/cCalMemData is asynchronous.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkOut.SyncIReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetLcl.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkOut.SyncIReset/c1ResetFromOClk.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetLcl.  Adding 1 LUTs and 2 Flops to estimation.
WARNING: [Designutils-308] Using distributed memory since read port window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioCalMemory/cCalMemData is asynchronous.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cDone_n.  Adding 1 LUTs and 2 Flops to estimation.
WARNING: [Designutils-308] Using distributed memory since read port window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioCalMemory/cCalMemData is asynchronous.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cDone_n.  Adding 1 LUTs and 2 Flops to estimation.
WARNING: [Designutils-308] Using distributed memory since read port window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioCalMemory/cCalMemData is asynchronous.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cDone_n.  Adding 1 LUTs and 2 Flops to estimation.
WARNING: [Designutils-308] Using distributed memory since read port window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/Gen9213ModuleSpecific.cRioCalMemoryx/cCalMemData is asynchronous.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/cDone_n.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205CommSmx/GenerateSsClkShiftReg.CrioSourceSync/oMiso.  Adding 1 LUTs and 2 Flops to estimation.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cReset.  Adding 1 LUTs and 2 Flops to estimation.
WARNING: [Designutils-308] Using distributed memory since read port window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRioCalMemoryx/cCalMemData is asynchronous.
INFO: [Designutils-295] Found reset/set on shift register ending at window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cTrig.  Adding 0 LUTs and 1 Flops to estimation.
INFO: [Designutils-303] Reporting estimation...
INFO: [Designutils-284] Found 7 multiplexers consumed by BlockRAM ports
INFO: [Designutils-287] Found 3 registers consumed by BlockRAM ports
INFO: [Designutils-300] Optimized 1820 multiplexer trees
INFO: [Designutils-298] Merged 218 multiplexers with driving combinational logic
INFO: [Designutils-285] Found 644 multiplexers used for register control logic
INFO: [Designutils-296] Inferred 45 shift registers using 45 SRL32s
INFO: [Designutils-275]      2-bit shift registers : 45
INFO: [Designutils-289] Found 79 registers consumed by IOBs
INFO: [Designutils-288] Found 6 registers consumed by DSP48s
INFO: [Designutils-297] Merged 1359 bitwise logic elements
INFO: [Designutils-283] Found 390 elements classified as dangling or disabled logic
INFO: [Designutils-282] Found 39 ROMs
WARNING: [Designutils-278] Estimation does not include 4 empty CellViews (see warnings)
INFO: [Designutils-277] Completed resource estimation on toplevel_gen - Slices: 9770, LUTs: 26184, Flops: 20089, BRAMs: 18, DSP48s: 6
INFO: [PlanAhead-261] Exiting PlanAhead...
INFO: [Common-83] Releasing license: PlanAhead
toplevel_gen 
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Adapter16.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_246.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_27.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataRd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataWr.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio80MhzClkRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9205ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9208IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213FxpScaleData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Initializer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SampleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResourceLogic.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ClockCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ErrorDecode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223HseioReadHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoNodeResHolder.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleSerializer.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleValidDelay.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403CommHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DiIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DioHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DoIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403LdHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SpiWord.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeDetection.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeIdentification.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCrcCheck.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiEeprom.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInitSequence.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInputFlops.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelectorControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiOutputMuxes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPicoBeatleInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPinConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPulseMask.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioClockCondition.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioParallelCrcCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioSourceSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForAnsteuerung_beenden_ctl_0RHFpgaRe
   adPortOnResbushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForMiteIoLikePortOnResInterface.vhd"
   into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTmax_ctl_5RHFpgaReadPortOnResbush
   old.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTopEnablesPortOnResTopEnablePassT
   hru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbFordinPortOnResSleep.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolVec.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSlvResetVal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopUnsigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DiagramReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaDisabler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteReadRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteWriteRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncAsyncInBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBoolAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSlAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainSM.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainWithTimeout.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FeedbackNonSctlCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoReadAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoWriteAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FloatingFeedbackGInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpAddSub.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivPreproc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivRnd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivSigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDynamicShift.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpNormalize.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpShiftCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/GenDataValid.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBaseResetCross.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/IDSel_Timer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Interface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/InvisibleResholder.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponent.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponentEnableChain.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaInput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaOutput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterfaceOutputEnables.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteIrq.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteReadInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteWriteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000001_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000012_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000020_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructure_64.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002e_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000032_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000041_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000042_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000004b_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000058_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000059_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005a_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005c_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000082_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008e_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008f_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000091_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000092_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000ac_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000bc_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000de_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000df_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e1_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e2_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e9_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000fb_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000010d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_Speichern4_dash_2FPGA.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbDelayer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbPowerOf2.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbRW.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbSerializeAccess.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOpNot.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaClockManagerControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaCtrlIndRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam_Inferred.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoClearControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoCountControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPopBuffer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPortReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFlipFlopFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaHostAccessibleRegister.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderRead.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderWrite.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLoopTimer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMergeErrors.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteReadInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteWriteInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPipelinedOrGateTreeSlv.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPulseSyncBaseWrapper.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegFrameworkShiftReg.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCoreBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaShiftReg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleModuloCounter.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaStockDcm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFixedToFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompareCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivideCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiplyCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixed.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixedCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandlerSlv.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiCycleEnableHandler.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFixedPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFloatingPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToInteger.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Divide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Equal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Greater.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32GreaterOrEqual.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Less.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32LessOrEqual.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Multiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32NotEqual.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommIntConfiguration.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommunicationInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9211Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9223Shared.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9403IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpArithmetic.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaArbiter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaCoresFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifoGenericValue.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaIrqRegisters.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaViControlRegister.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiLvPrims.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess32.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ResetSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SafeBusCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Sleep.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrInd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrIndOpt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SyncFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TheWindow.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TimeoutManager.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TopEnablePassThru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViSignature.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_132.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_173.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_185.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_189.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_202.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_136.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_175.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_187.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_232.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/bushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CommSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205ControlSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GenScanLine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SetTriggers.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SettingRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_SyncRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_io.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalReciprocal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMemory.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalParallelCrc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStock.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModuleId.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/forloop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_r_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_w_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMaxArray_vi_colon_Clone0.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMinArray_vi.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/whileloop.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl
INFO:TclTasksC:2116 - The automatic calculation of top has been turned-off.
   Please set the new top explicitly by running the "project set top" command.
   To re-calculate the new top automatically, set the "Auto Implementation Top"
   property to true.

Started : "Synthesize - XST".
Running xst...
Command Line: xst -intstyle ise -ifn "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.xst" -ofn "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.syr"
Reading design: toplevel_gen.prj
INFO:Xst - Part-select index evaluated to out of bound value may lead to incorrect synthesis results; it is recommended not to use them in RTL

=========================================================================
*                          HDL Parsing                                  *
=========================================================================
WARNING:Xst:2838 - Path definition '$XILINX/verilog/xst/nt/cpld_det_ver' in file C:/NIFPGA/programs/Xilinx13_4/ISE/vhdl/xst/nt/hdc.ini is invalid and being ignored.  Check the path and ensure that any environment variable specification is legal.
WARNING:Xst:2838 - Path definition '$XILINX/verilog/xst/nt/unimacro_ver' in file C:/NIFPGA/programs/Xilinx13_4/ISE/vhdl/xst/nt/hdc.ini is invalid and being ignored.  Check the path and ensure that any environment variable specification is legal.
WARNING:Xst:2838 - Path definition '$XILINX/verilog/xst/nt/unisim_ver' in file C:/NIFPGA/programs/Xilinx13_4/ISE/vhdl/xst/nt/hdc.ini is invalid and being ignored.  Check the path and ensure that any environment variable specification is legal.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiUtilities.vhd" into library work
Parsing package <PkgNiUtilities>.
Parsing package body <PkgNiUtilities>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgFxp.vhd" into library work
Parsing package <PkgFxp>.
Parsing package body <PkgFxp>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgFxpArithmetic.vhd" into library work
Parsing package <PkgFxpArithmetic>.
Parsing package body <PkgFxpArithmetic>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpShiftCore.vhd" into library work
Parsing entity <FxpShiftCore>.
Parsing architecture <rtl> of entity <fxpshiftcore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgFloat.vhd" into library work
Parsing package <PkgFloat>.
Parsing package body <PkgFloat>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpEnableHandlerSlv.vhd" into library work
Parsing entity <NiLvFxpEnableHandlerSlv>.
Parsing architecture <rtl> of entity <nilvfxpenablehandlerslv>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDynamicShift.vhd" into library work
Parsing entity <FxpDynamicShift>.
Parsing architecture <rtl> of entity <fxpdynamicshift>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlop.vhd" into library work
Parsing entity <DFlop>.
Parsing architecture <rtl> of entity <dflop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgGray.vhd" into library work
Parsing package <PkgGray>.
Parsing package body <PkgGray>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCcConstants.vhd" into library work
Parsing package <PkgCcConstants>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgBeatleSettings.vhd" into library work
Parsing package <PkgBeatleSettings>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpEnableHandler.vhd" into library work
Parsing entity <NiLvFxpEnableHandler>.
Parsing architecture <rtl> of entity <nilvfxpenablehandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatToFixedCore.vhd" into library work
Parsing entity <NiLvFloatToFixedCore>.
Parsing architecture <rtl> of entity <nilvfloattofixedcore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpNormalize.vhd" into library work
Parsing entity <FxpNormalize>.
Parsing architecture <rtl> of entity <fxpnormalize>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpAddSub.vhd" into library work
Parsing entity <FxpAddSub>.
Parsing architecture <rtl> of entity <fxpaddsub>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopSLV.vhd" into library work
Parsing entity <DFlopSLV>.
Parsing architecture <rtl> of entity <dflopslv>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgRegs.vhd" into library work
Parsing package <PkgRegs>.
Parsing package body <PkgRegs>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiLvPrims.vhd" into library work
Parsing package <PkgNiLvPrims>.
Parsing package body <PkgNiLvPrims>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgGlobalConst.vhd" into library work
Parsing package <PkgGlobalConst>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgFxpDivide.vhd" into library work
Parsing package <PkgFxpDivide>.
Parsing package body <PkgFxpDivide>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCartridge.vhd" into library work
Parsing package <PkgCartridge>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgBeatleTypedefs.vhd" into library work
Parsing package <PkgBeatleTypedefs>.
Parsing package body <PkgBeatleTypedefs>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpCoerce.vhd" into library work
Parsing entity <NiLvFxpCoerce>.
Parsing architecture <rtl> of entity <nilvfxpcoerce>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatToFixed.vhd" into library work
Parsing entity <NiLvFloatToFixed>.
Parsing architecture <rtl> of entity <nilvfloattofixed>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFixedToFloat.vhd" into library work
Parsing entity <NiLvFixedToFloat>.
Parsing architecture <rtl> of entity <nilvfixedtofloat>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivRnd.vhd" into library work
Parsing entity <FxpDivRnd>.
Parsing architecture <rtl> of entity <fxpdivrnd>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivPreproc.vhd" into library work
Parsing entity <FxpDivPreproc>.
Parsing architecture <rtl> of entity <fxpdivpreproc>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivInt.vhd" into library work
Parsing entity <FxpDivInt>.
Parsing architecture <rtl> of entity <fxpdivint>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopUnsigned.vhd" into library work
Parsing entity <DFlopUnsigned>.
Parsing architecture <rtl> of entity <dflopunsigned>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopGray.vhd" into library work
Parsing entity <DFlopGray>.
Parsing architecture <rtl> of entity <dflopgray>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopBoolVec.vhd" into library work
Parsing entity <DFlopBoolVec>.
Parsing architecture <rtl> of entity <dflopboolvec>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SyncFifoFlags.vhd" into library work
Parsing entity <SyncFifoFlags>.
Parsing architecture <rtl> of entity <syncfifoflags>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PulseSyncBase.vhd" into library work
Parsing entity <PulseSyncBase>.
Parsing architecture <behavior> of entity <pulsesyncbase>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrioInterface.vhd" into library work
Parsing package <PkgCrioInterface>.
Parsing package body <PkgCrioInterface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCommIntConfiguration.vhd" into library work
Parsing package <PkgCommIntConfiguration>.
Parsing package body <PkgCommIntConfiguration>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCcParameters.vhd" into library work
Parsing package <PkgCcParameters>.
Parsing package body <PkgCcParameters>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCcHsiSettings.vhd" into library work
Parsing package <PkgCcHsiSettings>.
Parsing package body <PkgCcHsiSettings>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvToInteger.vhd" into library work
Parsing entity <NiLvToInteger>.
Parsing architecture <rtl> of entity <nilvtointeger>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvToFloatingPoint.vhd" into library work
Parsing entity <NiLvToFloatingPoint>.
Parsing architecture <rtl> of entity <nilvtofloatingpoint>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvToFixedPoint.vhd" into library work
Parsing entity <NiLvToFixedPoint>.
Parsing architecture <rtl> of entity <nilvtofixedpoint>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaRegisterCoreBase.vhd" into library work
Parsing entity <NiFpgaRegisterCoreBase>.
Parsing architecture <rtl> of entity <nifpgaregistercorebase>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaDualPortRam_Inferred.vhd" into library work
Parsing entity <NiFpgaDualPortRAM_Inferred>.
Parsing architecture <rtl> of entity <nifpgadualportram_inferred>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\GenDataValid.vhd" into library work
Parsing entity <GenDataValid>.
Parsing architecture <rtl> of entity <gendatavalid>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivSigned.vhd" into library work
Parsing entity <FxpDivSigned>.
Parsing architecture <rtl> of entity <fxpdivsigned>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncAsyncInBase.vhd" into library work
Parsing entity <DoubleSyncAsyncInBase>.
Parsing architecture <rtl> of entity <doublesyncasyncinbase>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopSlvResetVal.vhd" into library work
Parsing entity <DFlopSlvResetVal>.
Parsing architecture <rtl> of entity <dflopslvresetval>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcSpiDither.vhd" into library work
Parsing entity <CcSpiDither>.
Parsing architecture <RTL> of entity <ccspidither>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcBarrelShifter.vhd" into library work
Parsing entity <CcBarrelShifter>.
Parsing architecture <rtl> of entity <ccbarrelshifter>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PulseSyncBool.vhd" into library work
Parsing entity <PulseSyncBool>.
Parsing architecture <behavior> of entity <pulsesyncbool>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaUtilities.vhd" into library work
Parsing package <PkgNiFpgaUtilities>.
Parsing package body <PkgNiFpgaUtilities>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaFifoGenericValue.vhd" into library work
Parsing package <PkgNiFpgaFifoGenericValue>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaCoresFifo.vhd" into library work
Parsing package <PkgNiFpgaCoresFifo>.
Parsing package body <PkgNiFpgaCoresFifo>.
WARNING:HDLCompiler:443 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaCoresFifo.vhd" Line 41: Function returnmitedmareadmode does not always return a value.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrioCommInt.vhd" into library work
Parsing package <PkgCrioCommInt>.
Parsing package body <PkgCrioCommInt>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9220.vhd" into library work
Parsing package <PkgCrio9220>.
Parsing package body <PkgCrio9220>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCommunicationInterface.vhd" into library work
Parsing package <PkgCommunicationInterface>.
Parsing package body <PkgCommunicationInterface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpMultiCycleEnableHandler.vhd" into library work
Parsing entity <NiLvFxpMultiCycleEnableHandler>.
Parsing architecture <rtl> of entity <nilvfxpmulticycleenablehandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatMultiplyCore.vhd" into library work
Parsing entity <NiLvFloatMultiplyCore>.
Parsing architecture <rtl> of entity <nilvfloatmultiplycore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatDivideCore.vhd" into library work
Parsing entity <NiLvFloatDivideCore>.
Parsing architecture <rtl> of entity <nilvfloatdividecore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvCoerce.vhd" into library work
Parsing entity <NiLvCoerce>.
Parsing architecture <rtl> of entity <nilvcoerce>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaRegisterCore.vhd" into library work
Parsing entity <NiFpgaRegisterCore>.
Parsing architecture <rtl> of entity <nifpgaregistercore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaPulseSyncBaseWrapper.vhd" into library work
Parsing entity <NiFpgaPulseSyncBaseWrapper>.
Parsing architecture <rtl> of entity <nifpgapulsesyncbasewrapper>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoFlags.vhd" into library work
Parsing entity <NiFpgaFifoFlags>.
Parsing architecture <rtl> of entity <nifpgafifoflags>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaDualPortRam.vhd" into library work
Parsing entity <NiFpgaDualPortRAM>.
Parsing architecture <rtl> of entity <nifpgadualportram>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\HandshakeBase.vhd" into library work
Parsing entity <HandshakeBase>.
Parsing architecture <behavior> of entity <handshakebase>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FxpDivCore.vhd" into library work
Parsing entity <FxpDivCore>.
Parsing architecture <rtl> of entity <fxpdivcore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncBase.vhd" into library work
Parsing entity <DoubleSyncBase>.
Parsing architecture <behavior> of entity <doublesyncbase>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopFallingEdge.vhd" into library work
Parsing entity <DFlopFallingEdge>.
Parsing architecture <rtl> of entity <dflopfallingedge>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcSpiDitherHardcodable.vhd" into library work
Parsing entity <CcSpiDitherHardcodable>.
Parsing architecture <RTL> of entity <ccspiditherhardcodable>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcSourceSynchFalling.vhd" into library work
Parsing entity <CcSourceSynchFalling>.
Parsing architecture <rtl> of entity <ccsourcesynchfalling>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcSourceSynch.vhd" into library work
Parsing entity <CcSourceSynch>.
Parsing architecture <rtl> of entity <ccsourcesynch>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcMuxSL4.vhd" into library work
Parsing entity <CcMuxSL4>.
Parsing architecture <RTL> of entity <ccmuxsl4>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcMuxSL3.vhd" into library work
Parsing entity <CcMuxSL3>.
Parsing architecture <RTL> of entity <ccmuxsl3>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcMuxSL2.vhd" into library work
Parsing entity <CcMuxSL2>.
Parsing architecture <RTL> of entity <ccmuxsl2>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsOutputLogic.vhd" into library work
Parsing entity <CcHsOutputLogic>.
Parsing architecture <RTL> of entity <cchsoutputlogic>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsInputLogic.vhd" into library work
Parsing entity <CcHsInputLogic>.
Parsing architecture <RTL> of entity <cchsinputlogic>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaFifo.vhd" into library work
Parsing package <PkgNiFpgaFifo>.
Parsing package body <PkgNiFpgaFifo>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaBoolOp.vhd" into library work
Parsing package <PkgNiFpgaBoolOp>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrioCiHsiEngine.vhd" into library work
Parsing package <PkgCrioCiHsiEngine>.
Parsing package body <PkgCrioCiHsiEngine>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrioCal.vhd" into library work
Parsing package <PkgCrioCal>.
Parsing package body <PkgCrioCal>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9403IoNode.vhd" into library work
Parsing package <PkgcRio9403IoNode>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9264Cal.vhd" into library work
Parsing package <PkgcRio9264Cal>.
Parsing package body <PkgcRio9264Cal>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9220Cal.vhd" into library work
Parsing package <PkgCrio9220Cal>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9213.vhd" into library work
Parsing package <PkgcRio9213>.
Parsing package body <PkgCrio9213>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9205.vhd" into library work
Parsing package <PkgcRio9205>.
Parsing package body <PkgcRio9205>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpMultiply.vhd" into library work
Parsing entity <NiLvFxpMultiply>.
Parsing architecture <rtl> of entity <nilvfxpmultiply>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpDivide.vhd" into library work
Parsing entity <NiLvFxpDivide>.
Parsing architecture <rtl> of entity <nilvfxpdivide>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatMultiply.vhd" into library work
Parsing entity <NiLvFloatMultiply>.
Parsing architecture <rtl> of entity <nilvfloatmultiply>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatDivide.vhd" into library work
Parsing entity <NiLvFloatDivide>.
Parsing architecture <rtl> of entity <nilvfloatdivide>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatCompareCore.vhd" into library work
Parsing entity <NiLvFloatCompareCore>.
Parsing architecture <rtl> of entity <nilvfloatcomparecore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFlipFlopFifo.vhd" into library work
Parsing entity <NiFpgaFlipFlopFifo>.
Parsing architecture <rtl> of entity <nifpgaflipflopfifo>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoPortReset.vhd" into library work
Parsing entity <NiFpgaFifoPortReset>.
Parsing architecture <rtl> of entity <nifpgafifoportreset>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifo.vhd" into library work
Parsing entity <NiFpgaFifo>.
Parsing architecture <rtl> of entity <nifpgafifo>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\HandshakeBool.vhd" into library work
Parsing entity <HandshakeBool>.
Parsing architecture <struct> of entity <handshakebool>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoWriteAdapter.vhd" into library work
Parsing entity <FifoWriteAdapter>.
Parsing architecture <rtl> of entity <fifowriteadapter>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoReadAdapter.vhd" into library work
Parsing entity <FifoReadAdapter>.
Parsing architecture <rtl> of entity <fiforeadadapter>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FeedbackNonSctlCore.vhd" into library work
Parsing entity <FeedbackNonSctlCore>.
Parsing architecture <rtl> of entity <feedbacknonsctlcore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncBool.vhd" into library work
Parsing entity <DoubleSyncBool>.
Parsing architecture <behavior> of entity <doublesyncbool>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DmaMiteWriteRegs.vhd" into library work
Parsing entity <DmaMiteWriteRegs>.
Parsing architecture <RTL> of entity <dmamitewriteregs>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DmaMiteReadRegs.vhd" into library work
Parsing entity <DmaMiteReadRegs>.
Parsing architecture <RTL> of entity <dmamitereadregs>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DmaDisabler.vhd" into library work
Parsing entity <DmaDisabler>.
Parsing architecture <rtl> of entity <dmadisabler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopBoolFallingEdge.vhd" into library work
Parsing entity <DFlopBoolFallingEdge>.
Parsing architecture <rtl> of entity <dflopboolfallingedge>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DFlopBool.vhd" into library work
Parsing entity <DFlopBool>.
Parsing architecture <rtl> of entity <dflopbool>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioParallelCrcCore.vhd" into library work
Parsing entity <CrioParallelCrcCore>.
Parsing architecture <rtl> of entity <crioparallelcrccore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiSpiConfig.vhd" into library work
Parsing entity <CrioCiSpiConfig>.
Parsing architecture <rtl> of entity <criocispiconfig>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiPinConfig.vhd" into library work
Parsing entity <CrioCiPinConfig>.
Parsing architecture <rtl> of entity <criocipinconfig>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiModeSelectorControl.vhd" into library work
Parsing entity <CrioCiModeSelectorControl>.
Parsing architecture <rtl> of entity <criocimodeselectorcontrol>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CpuDataWr.vhd" into library work
Parsing entity <CpuDataWr>.
Parsing architecture <rtl> of entity <cpudatawr>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CpuDataRd.vhd" into library work
Parsing entity <CpuDataRd>.
Parsing architecture <rtl> of entity <cpudatard>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcSpiLogic.vhd" into library work
Parsing entity <CcSpiLogic>.
Parsing architecture <rtl> of entity <ccspilogic>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcMuxSLN.vhd" into library work
Parsing entity <CcMuxSLN>.
Parsing architecture <RTL> of entity <ccmuxsln>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcInputFlop.vhd" into library work
Parsing entity <CcInputFlop>.
Parsing architecture <rtl> of entity <ccinputflop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsOutput.vhd" into library work
Parsing entity <CcHsOutput>.
Parsing architecture <RTL> of entity <cchsoutput>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcHsInput.vhd" into library work
Parsing entity <CcHsInput>.
Parsing architecture <RTL> of entity <cchsinput>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\TimeoutManager.vhd" into library work
Parsing entity <TimeoutManager>.
Parsing architecture <rtl> of entity <timeoutmanager>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ResetSync.vhd" into library work
Parsing entity <ResetSync>.
Parsing architecture <rtl> of entity <resetsync>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PulseSyncSL.vhd" into library work
Parsing entity <PulseSyncSL>.
Parsing architecture <behavior> of entity <pulsesyncsl>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9264.vhd" into library work
Parsing package <PkgcRio9264>.
Parsing package body <PkgcRio9264>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9213Cal.vhd" into library work
Parsing package <PkgcRio9213Cal>.
Parsing package body <PkgcRio9213Cal>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9211Cal.vhd" into library work
Parsing package <PkgcRio9211Cal>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9211.vhd" into library work
Parsing package <PkgCrio9211>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgcRio9205Cal.vhd" into library work
Parsing package <PkgcRio9205Cal>.
Parsing package body <PkgcRio9205Cal>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvMultiply.vhd" into library work
Parsing entity <NiLvMultiply>.
Parsing architecture <rtl> of entity <nilvmultiply>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpCompare.vhd" into library work
Parsing entity <NiLvFxpCompare>.
Parsing architecture <rtl> of entity <nilvfxpcompare>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatCompare.vhd" into library work
Parsing entity <NiLvFloatCompare>.
Parsing architecture <rtl> of entity <nilvfloatcompare>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvDivide.vhd" into library work
Parsing entity <NiLvDivide>.
Parsing architecture <rtl> of entity <nilvdivide>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaSimpleModuloCounter.vhd" into library work
Parsing entity <NiFpgaSimpleModuloCounter>.
Parsing architecture <rtl> of entity <nifpgasimplemodulocounter>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaSimpleCounter.vhd" into library work
Parsing entity <NiFpgaSimpleCounter>.
Parsing architecture <rtl> of entity <nifpgasimplecounter>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaShiftReg.vhd" into library work
Parsing entity <NiFpgaShiftReg>.
Parsing architecture <rtl> of entity <nifpgashiftreg>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaMiteWriteInterface.vhd" into library work
Parsing entity <NiFpgaMiteWriteInterface>.
Parsing architecture <RTL> of entity <nifpgamitewriteinterface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaMiteReadInterface.vhd" into library work
Parsing entity <NiFpgaMiteReadInterface>.
Parsing architecture <RTL> of entity <nifpgamitereadinterface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaMergeErrors.vhd" into library work
Parsing entity <NiFpgaMergeErrors>.
Parsing architecture <rtl> of entity <nifpgamergeerrors>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaLocalResHolderWrite.vhd" into library work
Parsing entity <NiFpgaLocalResHolderWrite>.
Parsing architecture <rtl> of entity <nifpgalocalresholderwrite>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoPopBuffer.vhd" into library work
Parsing entity <NiFpgaFifoPopBuffer>.
Parsing architecture <rtl> of entity <nifpgafifopopbuffer>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoClearControl.vhd" into library work
Parsing entity <NiFpgaFifoClearControl>.
Parsing architecture <rtl> of entity <nifpgafifoclearcontrol>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaBoolOp.vhd" into library work
Parsing entity <NiFpgaBoolOp>.
Parsing architecture <rtl> of entity <nifpgaboolop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\HandshakeSLV.vhd" into library work
Parsing entity <HandshakeSLV>.
Parsing architecture <struct> of entity <handshakeslv>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FloatingFeedbackGInit.vhd" into library work
Parsing entity <FloatingFeedbackGInit>.
Parsing architecture <rtl> of entity <floatingfeedbackginit>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncSL.vhd" into library work
Parsing entity <DoubleSyncSL>.
Parsing architecture <behavior> of entity <doublesyncsl>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStockSpiEngine.vhd" into library work
Parsing entity <cRioStockSpiEngine>.
Parsing architecture <rtl> of entity <criostockspiengine>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStockModuleId.vhd" into library work
Parsing entity <cRioStockModuleId>.
Parsing architecture <rtl> of entity <criostockmoduleid>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStockModeSelector.vhd" into library work
Parsing entity <cRioStockModeSelector>.
Parsing architecture <rtl> of entity <criostockmodeselector>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStockEepromRead.vhd" into library work
Parsing entity <cRioStockEePromRead>.
Parsing architecture <rtl> of entity <criostockeepromread>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioSourceSync.vhd" into library work
Parsing entity <CrioSourceSync>.
Parsing architecture <rtl> of entity <criosourcesync>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioEepromRead.vhd" into library work
Parsing entity <CrioEepromRead>.
Parsing architecture <rtl> of entity <crioeepromread>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiSpiEngine.vhd" into library work
Parsing entity <CrioCiSpiEngine>.
Parsing architecture <rtl> of entity <criocispiengine>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiPulseMask.vhd" into library work
Parsing entity <CrioCiPulseMask>.
Parsing architecture <rtl> of entity <criocipulsemask>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiPicoBeatleInit.vhd" into library work
Parsing entity <CrioCiPicoBeatleInit>.
Parsing architecture <rtl> of entity <criocipicobeatleinit>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiOutputMuxes.vhd" into library work
Parsing entity <CrioCiOutputMuxes>.
Parsing architecture <struct> of entity <criocioutputmuxes>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiModeSelector.vhd" into library work
Parsing entity <CrioCiModeSelector>.
Parsing architecture <struct> of entity <criocimodeselector>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiInputFlops.vhd" into library work
Parsing entity <CrioCiInputFlops>.
Parsing architecture <rtl> of entity <criociinputflops>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiInitSequence.vhd" into library work
Parsing entity <CrioCiInitSequence>.
Parsing architecture <rtl> of entity <criociinitsequence>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiHsiEngine.vhd" into library work
Parsing entity <CrioCiHsiEngine>.
Parsing architecture <rtl> of entity <criocihsiengine>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiEeprom.vhd" into library work
Parsing entity <CrioCiEeprom>.
Parsing architecture <rtl> of entity <criocieeprom>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiCrcCheck.vhd" into library work
Parsing entity <CrioCiCrcCheck>.
Parsing architecture <rtl> of entity <criocicrccheck>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiCartridgeIdentification.vhd" into library work
Parsing entity <CrioCiCartridgeIdentification>.
Parsing architecture <rtl> of entity <criocicartridgeidentification>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiCartridgeDetection.vhd" into library work
Parsing entity <CrioCiCartridgeDetection>.
Parsing architecture <rtl> of entity <criocicartridgedetection>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403SpiWord.vhd" into library work
Parsing entity <cRio9403SpiWord>.
Parsing architecture <rtl> of entity <crio9403spiword>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403LdHandler.vhd" into library work
Parsing entity <cRio9403LdHandler>.
Parsing architecture <rtl> of entity <crio9403ldhandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403DoIoNode.vhd" into library work
Parsing entity <Crio9403DoIoNode>.
Parsing architecture <behavioral> of entity <crio9403doionode>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403DioHandler.vhd" into library work
Parsing entity <cRio9403DioHandler>.
Parsing architecture <rtl> of entity <crio9403diohandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403DiIoNode.vhd" into library work
Parsing entity <Crio9403DiIoNode>.
Parsing architecture <behavioral> of entity <crio9403diionode>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9264IoNode.vhd" into library work
Parsing entity <Crio9264IoNode>.
Parsing architecture <rtl> of entity <crio9264ionode>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264CalReciprocal.vhd" into library work
Parsing entity <cRio9264CalReciprocal>.
Parsing architecture <rtl> of entity <crio9264calreciprocal>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223IoNodeResHolder.vhd" into library work
Parsing entity <Crio9223IoNodeResHolder>.
Parsing architecture <rtl> of entity <crio9223ionoderesholder>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220GetCalConst.vhd" into library work
Parsing entity <Crio9220GetCalConst>.
Parsing architecture <rtl> of entity <crio9220getcalconst>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213IoNode.vhd" into library work
Parsing entity <Crio9213IoNode>.
Parsing architecture <behavioral> of entity <crio9213ionode>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211IoNode.vhd" into library work
Parsing entity <Crio9211IoNode>.
Parsing architecture <behavioral> of entity <crio9211ionode>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205_io.vhd" into library work
Parsing entity <cRio9205_io>.
Parsing architecture <behavioral> of entity <crio9205_io>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205GenScanLine.vhd" into library work
Parsing entity <cRio9205GenScanLine>.
Parsing architecture <rtl> of entity <crio9205genscanline>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_202.vhd" into library work
Parsing entity <arrayLpIndx_202>.
Parsing architecture <rtl> of entity <arraylpindx_202>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_189.vhd" into library work
Parsing entity <arrayLpIndx_189>.
Parsing architecture <rtl> of entity <arraylpindx_189>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_185.vhd" into library work
Parsing entity <arrayLpIndx_185>.
Parsing architecture <rtl> of entity <arraylpindx_185>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_173.vhd" into library work
Parsing entity <arrayLpIndx_173>.
Parsing architecture <rtl> of entity <arraylpindx_173>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_132.vhd" into library work
Parsing entity <arrayLpIndx_132>.
Parsing architecture <rtl> of entity <arraylpindx_132>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arraycollect_232.vhd" into library work
Parsing entity <arraycollect_232>.
Parsing architecture <rtl> of entity <arraycollect_232>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arraycollect_187.vhd" into library work
Parsing entity <arraycollect_187>.
Parsing architecture <rtl> of entity <arraycollect_187>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arraycollect_175.vhd" into library work
Parsing entity <arraycollect_175>.
Parsing architecture <rtl> of entity <arraycollect_175>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arraycollect_136.vhd" into library work
Parsing entity <arraycollect_136>.
Parsing architecture <rtl> of entity <arraycollect_136>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\RegisterAccess32.vhd" into library work
Parsing entity <RegisterAccess32>.
Parsing architecture <rtl> of entity <registeraccess32>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaIrqRegisters.vhd" into library work
Parsing package <PkgNiFpgaIrqRegisters>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgCrio9223Shared.vhd" into library work
Parsing package <PkgCrio9223Shared>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvCompare.vhd" into library work
Parsing entity <NiLvCompare>.
Parsing architecture <rtl> of entity <nilvcompare>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaLoopTimer.vhd" into library work
Parsing entity <NiFpgaLoopTimer>.
Parsing architecture <rtl> of entity <nifpgalooptimer>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoCountControl.vhd" into library work
Parsing entity <NiFpgaFifoCountControl>.
Parsing architecture <rtl> of entity <nifpgafifocountcontrol>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaBoolOpNot.vhd" into library work
Parsing entity <NiFpgaBoolOpNot>.
Parsing architecture <rtl> of entity <nifpgaboolopnot>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e9_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_000000e9_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000e9_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e2_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000e2_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000e2_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000c8_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000c8_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000c8_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000c4_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000c4_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000c4_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000c0_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000c0_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000c0_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000bc_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000bc_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000bc_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000b8_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000b8_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000b8_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000b4_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000b4_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000b4_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000b0_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000b0_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000b0_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000ac_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000ac_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000ac_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000092_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_00000092_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000092_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000082_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_00000082_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000082_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005d_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_0000005d_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000005d_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002d_CaseStructure_64.vhd" into library work
Parsing entity <NiFpgaAG_0000002d_CaseStructure_64>.
Parsing architecture <vhdl_modgen> of entity <nifpgaag_0000002d_casestructure_64>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000021_CaseStructureFrame_0001.vhd" into library work
Parsing entity <NiFpgaAG_00000021_CaseStructureFrame_0001>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000021_casestructureframe_0001>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000021_CaseStructureFrame_0000.vhd" into library work
Parsing entity <NiFpgaAG_00000021_CaseStructureFrame_0000>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000021_casestructureframe_0000>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000013_CaseStructureFrame_0001.vhd" into library work
Parsing entity <NiFpgaAG_00000013_CaseStructureFrame_0001>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000013_casestructureframe_0001>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000013_CaseStructureFrame_0000.vhd" into library work
Parsing entity <NiFpgaAG_00000013_CaseStructureFrame_0000>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000013_casestructureframe_0000>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaOutput.vhd" into library work
Parsing entity <MiteDmaOutput>.
Parsing architecture <rtl> of entity <mitedmaoutput>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaInput.vhd" into library work
Parsing entity <MiteDmaInput>.
Parsing architecture <rtl> of entity <mitedmainput>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaComponentEnableChain.vhd" into library work
Parsing entity <MiteDmaComponentEnableChain>.
Parsing architecture <rtl> of entity <mitedmacomponentenablechain>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\HandshakeBaseResetCross.vhd" into library work
Parsing entity <HandshakeBaseResetCross>.
Parsing architecture <rtl> of entity <handshakebaseresetcross>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\forloop.vhd" into library work
Parsing entity <forloop>.
Parsing architecture <rtl> of entity <forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\EnableChainSM.vhd" into library work
Parsing entity <EnableChainSM>.
Parsing architecture <rtl> of entity <enablechainsm>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncSlAsyncIn.vhd" into library work
Parsing entity <DoubleSyncSlAsyncIn>.
Parsing architecture <rtl> of entity <doublesyncslasyncin>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioStock.vhd" into library work
Parsing entity <cRioStock>.
Parsing architecture <rtl> of entity <criostock>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCommInt.vhd" into library work
Parsing entity <CrioCommInt>.
Parsing architecture <rtl> of entity <criocommint>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioCalParallelCrc.vhd" into library work
Parsing entity <cRioCalParallelCrc>.
Parsing architecture <rtl> of entity <criocalparallelcrc>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioCalMultiply.vhd" into library work
Parsing entity <cRioCalMultiply>.
Parsing architecture <rtl> of entity <criocalmultiply>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRioCalMemory.vhd" into library work
Parsing entity <cRioCalMemory>.
Parsing architecture <rtl> of entity <criocalmemory>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403EnableChainHandler.vhd" into library work
Parsing entity <cRio9403EnableChainHandler>.
Parsing architecture <rtl> of entity <crio9403enablechainhandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403CommHandler.vhd" into library work
Parsing entity <cRio9403CommHandler>.
Parsing architecture <rtl> of entity <crio9403commhandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264UpdateHandler.vhd" into library work
Parsing entity <cRio9264UpdateHandler>.
Parsing architecture <rtl> of entity <crio9264updatehandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264IoHandler.vhd" into library work
Parsing entity <cRio9264IoHandler>.
Parsing architecture <rtl> of entity <crio9264iohandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264GetCalConst.vhd" into library work
Parsing entity <cRio9264GetCalConst>.
Parsing architecture <rtl> of entity <crio9264getcalconst>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264EnableChainHandler.vhd" into library work
Parsing entity <cRio9264EnableChainHandler>.
Parsing architecture <rtl> of entity <crio9264enablechainhandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264CalData.vhd" into library work
Parsing entity <cRio9264CalData>.
Parsing architecture <rtl> of entity <crio9264caldata>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223SampleValidDelay.vhd" into library work
Parsing entity <Crio9223SampleValidDelay>.
Parsing architecture <rtl> of entity <crio9223samplevaliddelay>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223SampleSerializer.vhd" into library work
Parsing entity <Crio9223SampleSerializer>.
Parsing architecture <rtl> of entity <crio9223sampleserializer>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223IoHandler.vhd" into library work
Parsing entity <Crio9223IoHandler>.
Parsing architecture <rtl> of entity <crio9223iohandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223HseioReadHandler.vhd" into library work
Parsing entity <Crio9223HseioReadHandler>.
Parsing architecture <rtl> of entity <crio9223hseioreadhandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223ErrorDecode.vhd" into library work
Parsing entity <Crio9223ErrorDecode>.
Parsing architecture <rtl> of entity <crio9223errordecode>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223EnableChainHandler.vhd" into library work
Parsing entity <Crio9223EnableChainHandler>.
Parsing architecture <rtl> of entity <crio9223enablechainhandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9223ClockCrossing.vhd" into library work
Parsing entity <Crio9223ClockCrossing>.
Parsing architecture <rtl> of entity <crio9223clockcrossing>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220SampleCounter.vhd" into library work
Parsing entity <Crio9220SampleCounter>.
Parsing architecture <rtl> of entity <crio9220samplecounter>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220Initializer.vhd" into library work
Parsing entity <Crio9220Initializer>.
Parsing architecture <rtl> of entity <crio9220initializer>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220CalData.vhd" into library work
Parsing entity <Crio9220CalData>.
Parsing architecture <rtl> of entity <crio9220caldata>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213UpdateHandler.vhd" into library work
Parsing entity <cRio9213UpdateHandler>.
Parsing architecture <rtl> of entity <crio9213updatehandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213IoHandler.vhd" into library work
Parsing entity <cRio9213IoHandler>.
Parsing architecture <rtl> of entity <crio9213iohandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213GetCalConst.vhd" into library work
Parsing entity <Crio9213GetCalConst>.
Parsing architecture <rtl> of entity <crio9213getcalconst>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213FxpScaleData.vhd" into library work
Parsing entity <Crio9213FxpScaleData>.
Parsing architecture <rtl> of entity <crio9213fxpscaledata>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213EnableChainHandler.vhd" into library work
Parsing entity <Crio9213EnableChainHandler>.
Parsing architecture <rtl> of entity <crio9213enablechainhandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211IoHandler.vhd" into library work
Parsing entity <Crio9211IoHandler>.
Parsing architecture <rtl> of entity <crio9211iohandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211GetCalConst.vhd" into library work
Parsing entity <Crio9211GetCalConst>.
Parsing architecture <rtl> of entity <crio9211getcalconst>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211EnableChainHandler.vhd" into library work
Parsing entity <Crio9211EnableChainHandler>.
Parsing architecture <rtl> of entity <crio9211enablechainhandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211CalData.vhd" into library work
Parsing entity <cRio9211CalData>.
Parsing architecture <rtl> of entity <crio9211caldata>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9208IoHandler.vhd" into library work
Parsing entity <Crio9208IoHandler>.
Parsing architecture <rtl> of entity <crio9208iohandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205SetTriggers.vhd" into library work
Parsing entity <cRio9205SetTriggers>.
Parsing architecture <rtl> of entity <crio9205settriggers>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205SettingRegs.vhd" into library work
Parsing entity <cRio9205SettingRegs>.
Parsing architecture <rtl> of entity <crio9205settingregs>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205IoHandler.vhd" into library work
Parsing entity <cRio9205IoHandler>.
Parsing architecture <rtl> of entity <crio9205iohandler>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205GetCalConst.vhd" into library work
Parsing entity <cRio9205GetCalConst>.
Parsing architecture <rtl> of entity <crio9205getcalconst>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205ControlSm.vhd" into library work
Parsing entity <cRio9205ControlSm>.
Parsing architecture <rtl> of entity <crio9205controlsm>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205CommSm.vhd" into library work
Parsing entity <cRio9205CommSm>.
Parsing architecture <rtl> of entity <crio9205commsm>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205CalData.vhd" into library work
Parsing entity <cRio9205CalData>.
Parsing architecture <rtl> of entity <crio9205caldata>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ArrayIndexNode_27.vhd" into library work
Parsing entity <ArrayIndexNode_27>.
Parsing architecture <rtl> of entity <arrayindexnode_27>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ArrayIndexNode_246.vhd" into library work
Parsing entity <ArrayIndexNode_246>.
Parsing architecture <rtl> of entity <arrayindexnode_246>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Adapter16.vhd" into library work
Parsing entity <Adapter16>.
Parsing architecture <rtl> of entity <adapter16>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SubVICtlOrIndOpt.vhd" into library work
Parsing entity <SubVICtlOrIndOpt>.
Parsing architecture <rtl> of entity <subvictlorindopt>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SubVICtlOrInd.vhd" into library work
Parsing entity <SubVICtlOrInd>.
Parsing architecture <rtl> of entity <subvictlorind>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\resholder_w_opt.vhd" into library work
Parsing entity <resholder_w_opt>.
Parsing architecture <rtl> of entity <resholder_w_opt>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\resholder_r_opt.vhd" into library work
Parsing entity <resholder_r_opt>.
Parsing architecture <rtl> of entity <resholder_r_opt>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\RegisterAccess.vhd" into library work
Parsing entity <RegisterAccess>.
Parsing architecture <rtl> of entity <registeraccess>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaLocalResHolderRead.vhd" into library work
Parsing entity <NiFpgaLocalResHolderRead>.
Parsing architecture <rtl> of entity <nifpgalocalresholderread>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbPowerOf2.vhd" into library work
Parsing entity <NiFpgaArbPowerOf2>.
Parsing architecture <rtl> of entity <nifpgaarbpowerof2>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e1_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_000000e1_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000e1_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000df_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_000000df_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000df_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_00000091_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000091_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000008f_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_0000008f_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000008f_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005c_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_0000005c_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000005c_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005a_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_0000005a_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000005a_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000032_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_00000032_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000032_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002e_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_0000002e_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000002e_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000020_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_00000020_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000020_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000012_ForLoop.vhd" into library work
Parsing entity <NiFpgaAG_00000012_ForLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000012_forloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteWriteInterface.vhd" into library work
Parsing entity <MiteWriteInterface>.
Parsing architecture <RTL> of entity <mitewriteinterface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteReadInterface.vhd" into library work
Parsing entity <MiteReadInterface>.
Parsing architecture <RTL> of entity <mitereadinterface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteIrq.vhd" into library work
Parsing entity <MiteIrq>.
Parsing architecture <rtl> of entity <miteirq>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteInterfaceOutputEnables.vhd" into library work
Parsing entity <MiteInterfaceOutputEnables>.
Parsing architecture <rtl> of entity <miteinterfaceoutputenables>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaComponent.vhd" into library work
Parsing entity <MiteDmaComponent>.
Parsing architecture <rtl> of entity <mitedmacomponent>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DoubleSyncBoolAsyncIn.vhd" into library work
Parsing entity <DoubleSyncBoolAsyncIn>.
Parsing architecture <rtl> of entity <doublesyncboolasyncin>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403.vhd" into library work
Parsing entity <cRio9403>.
Parsing architecture <rtl> of entity <crio9403>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9264.vhd" into library work
Parsing entity <cRio9264>.
Parsing architecture <rtl> of entity <crio9264>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220.vhd" into library work
Parsing entity <Crio9220>.
Parsing architecture <rtl> of entity <crio9220>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213.vhd" into library work
Parsing entity <Crio9213>.
Parsing architecture <rtl> of entity <crio9213>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211.vhd" into library work
Parsing entity <Crio9211>.
Parsing architecture <rtl> of entity <crio9211>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205.vhd" into library work
Parsing entity <cRio9205>.
Parsing architecture <rtl> of entity <crio9205>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\whileloop.vhd" into library work
Parsing entity <whileloop>.
Parsing architecture <rtl> of entity <whileloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\subMinArray_vi.vhd" into library work
Parsing entity <subMinArray_vi>.
Parsing architecture <vhdl_labview> of entity <subminarray_vi>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\subMaxArray_vi_colon_Clone0.vhd" into library work
Parsing entity <subMaxArray_vi_colon_Clone0>.
Parsing architecture <vhdl_labview> of entity <submaxarray_vi_colon_clone0>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SafeBusCrossing.vhd" into library work
Parsing entity <SafeBusCrossing>.
Parsing architecture <rtl> of entity <safebuscrossing>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgRegister.vhd" into library work
Parsing package <PkgRegister>.
Parsing package body <PkgRegister>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaViControlRegister.vhd" into library work
Parsing package <PkgNiFpgaViControlRegister>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaArbiter.vhd" into library work
Parsing package <PkgNiFpgaArbiter>.
Parsing package body <PkgNiFpgaArbiter>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaRegFrameworkShiftReg.vhd" into library work
Parsing entity <NiFpgaRegFrameworkShiftReg>.
Parsing architecture <rtl> of entity <nifpgaregframeworkshiftreg>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaHostAccessibleRegister.vhd" into library work
Parsing entity <NiFpgaHostAccessibleRegister>.
Parsing architecture <rtl> of entity <nifpgahostaccessibleregister>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbSerializeAccess.vhd" into library work
Parsing entity <NiFpgaArbSerializeAccess>.
Parsing architecture <rtl> of entity <nifpgaarbserializeaccess>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbDelayer.vhd" into library work
Parsing entity <NiFpgaArbDelayer>.
Parsing architecture <rtl> of entity <nifpgaarbdelayer>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000fb_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_000000fb_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000fb_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000de_WhileLoop.vhd" into library work
Parsing entity <NiFpgaAG_000000de_WhileLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_000000de_whileloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000008e_WhileLoop.vhd" into library work
Parsing entity <NiFpgaAG_0000008e_WhileLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000008e_whileloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000059_WhileLoop.vhd" into library work
Parsing entity <NiFpgaAG_00000059_WhileLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000059_whileloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000004b_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_0000004b_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000004b_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000042_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_00000042_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000042_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd" into library work
Parsing entity <NiFpgaAG_0000002d_CaseStructureFrame_0001>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000002d_casestructureframe_0001>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd" into library work
Parsing entity <NiFpgaAG_0000002d_CaseStructureFrame_0000>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000002d_casestructureframe_0000>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000001_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_00000001_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000001_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteInterface.vhd" into library work
Parsing entity <MiteInterface>.
Parsing architecture <rtl> of entity <miteinterface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403ResourceCore.vhd" into library work
Parsing entity <Crio9403ResourceCore>.
Parsing architecture <behavioral> of entity <crio9403resourcecore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9264ResourceCore.vhd" into library work
Parsing entity <Crio9264ResourceCore>.
Parsing architecture <struct> of entity <crio9264resourcecore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220SyncResourceLogic.vhd" into library work
Parsing entity <Crio9220SyncResourceLogic>.
Parsing architecture <rtl> of entity <crio9220syncresourcelogic>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220ResourceCore.vhd" into library work
Parsing entity <Crio9220ResourceCore>.
Parsing architecture <struct> of entity <crio9220resourcecore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213ResourceCore.vhd" into library work
Parsing entity <Crio9213ResourceCore>.
Parsing architecture <struct> of entity <crio9213resourcecore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211ResourceCore.vhd" into library work
Parsing entity <Crio9211ResourceCore>.
Parsing architecture <struct> of entity <crio9211resourcecore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9205ResourceCore.vhd" into library work
Parsing entity <Crio9205ResourceCore>.
Parsing architecture <struct> of entity <crio9205resourcecore>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ViSignature.vhd" into library work
Parsing entity <ViSignature>.
Parsing architecture <rtl> of entity <visignature>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ViControl.vhd" into library work
Parsing entity <ViControl>.
Parsing architecture <rtl> of entity <vicontrol>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\TopEnablePassThru.vhd" into library work
Parsing entity <TopEnablePassThru>.
Parsing architecture <rtl> of entity <topenablepassthru>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Sleep.vhd" into library work
Parsing entity <Sleep>.
Parsing architecture <behavioral> of entity <sleep>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaCtrlIndRegister.vhd" into library work
Parsing entity <NiFpgaCtrlIndRegister>.
Parsing architecture <rtl> of entity <nifpgactrlindregister>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaClockManagerControl.vhd" into library work
Parsing entity <NiFpgaClockManagerControl>.
Parsing architecture <rtl> of entity <nifpgaclockmanagercontrol>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" into library work
Parsing entity <NiFpgaArbRW>.
Parsing architecture <rtl> of entity <nifpgaarbrw>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000010d_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_0000010d_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_0000010d_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000058_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_00000058_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000058_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" into library work
Parsing entity <NiFpgaAG_00000041_SequenceFrame>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000041_sequenceframe>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000000_WhileLoop.vhd" into library work
Parsing entity <NiFpgaAG_00000000_WhileLoop>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_00000000_whileloop>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\InvisibleResholder.vhd" into library work
Parsing entity <InvisibleResholder>.
Parsing architecture <rtl> of entity <invisibleresholder>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" into library work
Parsing entity <Interface>.
Parsing architecture <rtl> of entity <interface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\IDSel_Timer.vhd" into library work
Parsing entity <IDSel_Timer>.
Parsing architecture <behavioral> of entity <idsel_timer>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DiagramReset.vhd" into library work
Parsing entity <DiagramReset>.
Parsing architecture <rtl> of entity <diagramreset>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForTopEnablesPortOnResTopEnablePassThru.vhd" into library work
Parsing entity <CustomArbForTopEnablesPortOnResTopEnablePassThru>.
Parsing architecture <rtl> of entity <customarbfortopenablesportonrestopenablepassthru>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForTmax_ctl_5RHFpgaReadPortOnResbushold.vhd" into library work
Parsing entity <CustomArbForTmax_ctl_5RHFpgaReadPortOnResbushold>.
Parsing architecture <rtl> of entity <customarbfortmax_ctl_5rhfpgareadportonresbushold>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForMiteIoLikePortOnResInterface.vhd" into library work
Parsing entity <CustomArbForMiteIoLikePortOnResInterface>.
Parsing architecture <rtl> of entity <customarbformiteiolikeportonresinterface>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbFordinPortOnResSleep.vhd" into library work
Parsing entity <CustomArbFordinPortOnResSleep>.
Parsing architecture <rtl> of entity <customarbfordinportonressleep>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForAnsteuerung_beenden_ctl_0RHFpgaReadPortOnResbushold.vhd" into library work
Parsing entity <CustomArbForAnsteuerung_beenden_ctl_0RHFpgaReadPortOnResbushold>.
Parsing architecture <rtl> of entity <customarbforansteuerung_beenden_ctl_0rhfpgareadportonresbushold>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403SyncResource.vhd" into library work
Parsing entity <Crio9403SyncResource>.
Parsing architecture <behavioral> of entity <crio9403syncresource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9403Resource.vhd" into library work
Parsing entity <Crio9403Resource>.
Parsing architecture <behavioral> of entity <crio9403resource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9264SyncResource.vhd" into library work
Parsing entity <Crio9264SyncResource>.
Parsing architecture <behavioral> of entity <crio9264syncresource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9264Resource.vhd" into library work
Parsing entity <Crio9264Resource>.
Parsing architecture <struct> of entity <crio9264resource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220SyncResource.vhd" into library work
Parsing entity <Crio9220SyncResource>.
Parsing architecture <struct> of entity <crio9220syncresource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9220Resource.vhd" into library work
Parsing entity <Crio9220Resource>.
Parsing architecture <struct> of entity <crio9220resource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213SyncResource.vhd" into library work
Parsing entity <Crio9213SyncResource>.
Parsing architecture <behavioral> of entity <crio9213syncresource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213Resource.vhd" into library work
Parsing entity <Crio9213Resource>.
Parsing architecture <struct> of entity <crio9213resource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211SyncResource.vhd" into library work
Parsing entity <Crio9211SyncResource>.
Parsing architecture <behavioral> of entity <crio9211syncresource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211Resource.vhd" into library work
Parsing entity <Crio9211Resource>.
Parsing architecture <struct> of entity <crio9211resource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205_SyncRes.vhd" into library work
Parsing entity <cRio9205_SyncRes>.
Parsing architecture <behavioral> of entity <crio9205_syncres>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205_Resource.vhd" into library work
Parsing entity <cRio9205_Resource>.
Parsing architecture <struct> of entity <crio9205_resource>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio80MhzClkRes.vhd" into library work
Parsing entity <Crio80MhzClkRes>.
Parsing architecture <struct> of entity <crio80mhzclkres>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\bushold.vhd" into library work
Parsing entity <bushold>.
Parsing architecture <rtl> of entity <bushold>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaStockDcm.vhd" into library work
Parsing entity <NiFpgaStockDcm>.
Parsing architecture <rtl> of entity <nifpgastockdcm>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_Speichern4_dash_2FPGA.vhd" into library work
Parsing entity <NiFpgaAG_Speichern4_dash_2FPGA>.
Parsing architecture <vhdl_labview> of entity <nifpgaag_speichern4_dash_2fpga>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\TheWindow.vhd" into library work
Parsing entity <TheWindow>.
Parsing architecture <behavioral> of entity <thewindow>.
Parsing VHDL file "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\toplevel_gen.vhd" into library work
Parsing entity <toplevel_gen>.
Parsing architecture <vhdl_modgen> of entity <toplevel_gen>.

=========================================================================
*                            HDL Elaboration                            *
=========================================================================

Elaborating entity <toplevel_gen> (architecture <vhdl_modgen>) from library <work>.

Elaborating entity <TheWindow> (architecture <behavioral>) from library <work>.

Elaborating entity <NiFpgaStockDcm> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaClockManagerControl> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaClockManagerControl.vhd" Line 331. Case statement is complete. others clause is never selected

Elaborating entity <DoubleSyncBoolAsyncIn> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DoubleSyncSlAsyncIn> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DoubleSyncAsyncInBase> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBool> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\TheWindow.vhd" Line 494: <bufg> remains a black-box since it has no binding entity.

Elaborating entity <NiFpgaAG_Speichern4_dash_2FPGA> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_00000000_WhileLoop> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000000_WhileLoop.vhd" Line 119: Using initial value "000000000000000000000000000000000" for output_15 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000000_WhileLoop.vhd" Line 143: Using initial value "0" for s_constant_3877 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000000_WhileLoop.vhd" Line 150: Using initial value "00111100" for s_maxtemperaturzelle_3869 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000000_WhileLoop.vhd" Line 151: Using initial value "000111011001100110011010" for s_maxspannungzelle_6105 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000000_WhileLoop.vhd" Line 160: Using initial value "101100000000000000000000" for s_y_6111 since it is never assigned

Elaborating entity <NiFpgaAG_00000001_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <Crio9223IoNodeResHolder> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaMergeErrors> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpEnableHandlerSlv> (architecture <rtl>) with generics from library <work>.

Elaborating entity <subMaxArray_vi_colon_Clone0> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\subMaxArray_vi_colon_Clone0.vhd" Line 26: Using initial value "00000000000000000000000000001110" for output since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\subMaxArray_vi_colon_Clone0.vhd" Line 29: Using initial value "00000000000000000000000000000000" for s_constant_260 since it is never assigned

Elaborating entity <resholder_r_opt> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_00000012_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaShiftReg> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ArrayIndexNode_27> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvCompare> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCompare> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFxpCompare.vhd" Line 92: Using initial value "0" for cdummyfxp since it is never assigned

Elaborating entity <NiLvFxpEnableHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpEnableHandlerSlv> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_0000002d_CaseStructure_64> (architecture <vhdl_modgen>) from library <work>.

Elaborating entity <NiFpgaAG_00000013_CaseStructureFrame_0000> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_00000013_CaseStructureFrame_0001> (architecture <vhdl_labview>) from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000012_ForLoop.vhd" Line 212. Case statement is complete. others clause is never selected

Elaborating entity <forloop> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\forloop.vhd" Line 52: Range is empty (null range)
WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\forloop.vhd" Line 199: Assignment ignored

Elaborating entity <resholder_w_opt> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SubVICtlOrIndOpt> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SubVICtlOrIndOpt> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SubVICtlOrInd> (architecture <rtl>) with generics from library <work>.

Elaborating entity <subMinArray_vi> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\subMinArray_vi.vhd" Line 25: Using initial value "00000000000000000000000000001110" for output since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\subMinArray_vi.vhd" Line 28: Using initial value "00000000000000000000000000000000" for s_constant_211 since it is never assigned

Elaborating entity <NiFpgaAG_00000020_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiLvCompare> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCompare> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_00000021_CaseStructureFrame_0000> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_00000021_CaseStructureFrame_0001> (architecture <vhdl_labview>) from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000020_ForLoop.vhd" Line 212. Case statement is complete. others clause is never selected

Elaborating entity <FloatingFeedbackGInit> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FeedbackNonSctlCore> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaRegisterCore> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaRegisterCoreBase> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLocalResHolderRead> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvCompare> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCompare> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaBoolOp> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvToInteger> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpCoerce> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpEnableHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpEnableHandlerSlv> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLocalResHolderWrite> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_0000002d_CaseStructureFrame_0000> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd" Line 29: Using initial value "00101000000000000000" for s_mod6_slash_ao_7599 since it is never assigned

Elaborating entity <NiFpgaAG_0000002e_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <Crio9264IoNode> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaMergeErrors> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_0000002d_CaseStructureFrame_0001> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd" Line 29: Using initial value "00000000000000000000" for s_mod6_slash_ao_7582 since it is never assigned

Elaborating entity <NiFpgaAG_00000032_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000000_WhileLoop.vhd" Line 650. Case statement is complete. others clause is never selected

Elaborating entity <whileloop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_00000041_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 80: Using initial value "000000000000000000000000000000000" for output_7 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 87: Using initial value "000000000000000000000000000000000" for output_14 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 88: Using initial value "0" for s_ansteuerung_beenden_6099 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 93: Using initial value "0" for s_constant_2685 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 94: Using initial value "1" for s_mod3_slash_dio_2682 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 95: Using initial value "0" for s_mod3_slash_dio_2679 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 96: Using initial value "0" for s_mod3_slash_dio_2675 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 99: Using initial value "0" for s_constant_1798 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 100: Using initial value "1" for s_mod3_slash_dio_549 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 101: Using initial value "0" for s_mod3_slash_dio_2373 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000041_SequenceFrame.vhd" Line 102: Using initial value "0" for s_mod3_slash_dio_2440 since it is never assigned

Elaborating entity <NiFpgaAG_00000042_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <Crio9403DoIoNode> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <NiFpgaMergeErrors> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_0000004b_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_00000058_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000058_SequenceFrame.vhd" Line 389: Using initial value "0" for s_lastausge4nge_aktiv_setzen_2793 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000058_SequenceFrame.vhd" Line 392: Using initial value "00000000000000000000" for s_strom_quelle_2781 since it is never assigned

Elaborating entity <NiFpgaAG_00000059_WhileLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaLocalResHolderRead> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_0000005a_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005a_SequenceFrame.vhd" Line 23: Using initial value "00000000000000000000001111101000" for s_aufnahmezeit_temp_ms_1482 since it is never assigned

Elaborating entity <NiFpgaLoopTimer> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaSimpleModuloCounter> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:92 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaSimpleModuloCounter.vhd" Line 41: cenable should be on the sensitivity list of the process

Elaborating entity <NiFpgaAG_0000005c_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005c_SequenceFrame.vhd" Line 166: Using initial value "00000000000000000000000000100010" for output since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000005c_SequenceFrame.vhd" Line 201: Using initial value "000000000000000000000000000000000" for output_36 since it is never assigned

Elaborating entity <NiFpgaAG_0000005d_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <Crio9211IoNode> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9213IoNode> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <NiFpgaMergeErrors> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLocalResHolderWrite> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_00000082_ForLoop> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000082_ForLoop.vhd" Line 35: Using initial value "000000000000000000000000000000000" for output_2 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000082_ForLoop.vhd" Line 36: Using initial value "0" for s_constant_1419 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000082_ForLoop.vhd" Line 43: Using initial value "00000000000000000000000000000000" for s_timeout_1434 since it is never assigned

Elaborating entity <arrayLpIndx_132> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_132.vhd" Line 37: Assignment to zro ignored, since the identifier is never used

Elaborating entity <arraycollect_136> (architecture <rtl>) with generics from library <work>.

Elaborating entity <forloop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_0000008e_WhileLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_0000008f_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000008f_SequenceFrame.vhd" Line 23: Using initial value "00000000000000000000001111101000" for s_aufnahmezeit_daten_ms_11815 since it is never assigned

Elaborating entity <NiFpgaAG_00000091_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 130: Using initial value "00000000000000000000000000010111" for output since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 131: Using initial value "00000000000000000000000000001110" for output_2 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 132: Using initial value "00000000000000000000000000000011" for output_3 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 133: Using initial value "00000000000000000000000000000011" for output_4 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 134: Using initial value "00000000000000000000000000000011" for output_5 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 135: Using initial value "00000000000000000000000000000011" for output_6 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 136: Using initial value "00000000000000000000000000000011" for output_7 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 137: Using initial value "00000000000000000000000000000011" for output_8 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 161: Using initial value "000000000000000000000000000000000" for output_32 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 241: Using initial value "01000000110000000000000000000000" for s_y_3241 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 253: Using initial value "01000001001000000000000000000000" for s_y_3010 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_00000091_SequenceFrame.vhd" Line 265: Using initial value "00111011101001000000000000000000" for s_y_4343 since it is never assigned

Elaborating entity <NiFpgaAG_00000092_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <cRio9205_io> (architecture <behavioral>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiUtilities.vhd" Line 377: Range is empty (null range)

Elaborating entity <NiFpgaMergeErrors> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_000000ac_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <arrayLpIndx_173> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_173.vhd" Line 37: Assignment to zro ignored, since the identifier is never used

Elaborating entity <NiLvToFloatingPoint> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFixedToFloat> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FxpNormalize> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFxpEnableHandlerSlv> (architecture <rtl>) with generics from library <work>.

Elaborating entity <arraycollect_175> (architecture <rtl>) with generics from library <work>.

Elaborating entity <forloop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_000000b0_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_000000b4_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_000000b8_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <arrayLpIndx_185> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_185.vhd" Line 37: Assignment to zro ignored, since the identifier is never used

Elaborating entity <NiLvToFloatingPoint> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFixedToFloat> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FxpNormalize> (architecture <rtl>) with generics from library <work>.

Elaborating entity <arraycollect_187> (architecture <rtl>) with generics from library <work>.

Elaborating entity <forloop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLocalResHolderWrite> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_000000bc_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <arrayLpIndx_189> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_189.vhd" Line 37: Assignment to zro ignored, since the identifier is never used

Elaborating entity <NiLvMultiply> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFloatMultiply> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvToFloatingPoint> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFloatMultiplyCore> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatMultiplyCore.vhd" Line 52: <nilvxipfloat32multiply> remains a black-box since it has no binding entity.

Elaborating entity <NiLvCoerce> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvToFloatingPoint> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_000000c0_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_000000c4_ForLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiLvDivide> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFloatDivide> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvFloatDivideCore> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiLvFloatDivideCore.vhd" Line 52: <nilvxipfloat32divide> remains a black-box since it has no binding entity.

Elaborating entity <NiLvCoerce> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiLvToFloatingPoint> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLocalResHolderWrite> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_000000c8_ForLoop> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000c8_ForLoop.vhd" Line 37: Using initial value "0" for s_constant_1145 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000c8_ForLoop.vhd" Line 44: Using initial value "00000000000000000000000000000000" for s_timeout_1172 since it is never assigned

Elaborating entity <arrayLpIndx_202> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\arrayLpIndx_202.vhd" Line 37: Assignment to zro ignored, since the identifier is never used

Elaborating entity <forloop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaBoolOpNot> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_000000de_WhileLoop> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_000000df_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000df_SequenceFrame.vhd" Line 25: Using initial value "00000000000000000000001111101000" for s_ansteuerzeit_ms_11653 since it is never assigned

Elaborating entity <NiFpgaAG_000000e1_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e1_SequenceFrame.vhd" Line 72: Using initial value "00000000000000000000000000000100" for output_9 since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e1_SequenceFrame.vhd" Line 73: Using initial value "1" for s_lastausge4nge_aktiv_setzen_561 since it is never assigned

Elaborating entity <NiFpgaAG_000000e2_ForLoop> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_000000e2_ForLoop.vhd" Line 44: Using initial value "00000000000000000000000000000000" for s_timeout_5988 since it is never assigned

Elaborating entity <NiFpgaShiftReg> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FloatingFeedbackGInit> (architecture <rtl>) with generics from library <work>.

Elaborating entity <arraycollect_232> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ArrayIndexNode_246> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_000000e9_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <Crio9403DiIoNode> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <NiFpgaMergeErrors> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaLocalResHolderWrite> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaMergeErrors> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaAG_000000fb_SequenceFrame> (architecture <vhdl_labview>) from library <work>.

Elaborating entity <NiFpgaAG_0000010d_SequenceFrame> (architecture <vhdl_labview>) from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaAG_0000010d_SequenceFrame.vhd" Line 25: Using initial value "1" for s_reset_4054 since it is never assigned

Elaborating entity <NiFpgaLocalResHolderWrite> (architecture <rtl>) with generics from library <work>.

Elaborating entity <InvisibleResholder> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9220SyncResource> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9220SyncResourceLogic> (architecture <rtl>) with generics from library <work>.

Elaborating entity <TopEnablePassThru> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9264SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <bushold> (architecture <rtl>) with generics from library <work>.

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ResetSync> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBool> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlop> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBoolFallingEdge> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopFallingEdge> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ResetSync> (architecture <rtl>) with generics from library <work>.

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaRegFrameworkShiftReg> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DoubleSyncBoolAsyncIn> (architecture <rtl>) with generics from library <work>.

Elaborating entity <PulseSyncBool> (architecture <behavior>) from library <work>.

Elaborating entity <PulseSyncBase> (architecture <behavior>) from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\bushold.vhd" Line 784: Assignment to miteclkwidewrite ignored, since the identifier is never used

Elaborating entity <NiFpgaRegFrameworkShiftReg> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9403SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9403SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9211SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9211SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9213SyncResource> (architecture <behavioral>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213SyncResource.vhd" Line 177: Net <cAiChannelDataInt[31][23]> does not have a driver.

Elaborating entity <Interface> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 101: Using initial value (('U','U',"UUUUU")) for birqoutarray since it is never assigned
WARNING:HDLCompiler:871 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 103: Using initial value ("UU") for birqstatusoutarray since it is never assigned

Elaborating entity <MiteInterface> (architecture <rtl>) from library <work>.

Elaborating entity <MiteInterfaceOutputEnables> (architecture <rtl>) from library <work>.

Elaborating entity <RegisterAccess> (architecture <rtl>) with generics from library <work>.

Elaborating entity <RegisterAccess32> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteDmaComponent> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteDmaComponentEnableChain> (architecture <rtl>) with generics from library <work>.

Elaborating entity <TimeoutManager> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaComponentEnableChain.vhd" Line 221. Case statement is complete. others clause is never selected

Elaborating entity <NiFpgaFifoClearControl> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoClearControl.vhd" Line 229. Case statement is complete. others clause is never selected

Elaborating entity <DoubleSyncBool> (architecture <behavior>) from library <work>.

Elaborating entity <DoubleSyncBase> (architecture <behavior>) with generics from library <work>.

Elaborating entity <NiFpgaFifoPortReset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaPulseSyncBaseWrapper> (architecture <rtl>) from library <work>.

Elaborating entity <MiteDmaInput> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaMiteReadInterface> (architecture <RTL>) with generics from library <work>.

Elaborating entity <NiFpgaFifo> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SyncFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopUnsigned> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopGray> (architecture <rtl>) with generics from library <work>.

Elaborating entity <GenDataValid> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBoolVec> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSLV> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaDualPortRAM> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaDualPortRAM_Inferred> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FifoReadAdapter> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoReadAdapter.vhd" Line 87: Range is empty (null range)
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoReadAdapter.vhd" Line 195: Net <StallDisableBlk.cStallDisableLoc> does not have a driver.

Elaborating entity <HandshakeBool> (architecture <struct>) from library <work>.

Elaborating entity <HandshakeBase> (architecture <behavior>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DmaDisabler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CpuDataRd> (architecture <rtl>) from library <work>.

Elaborating entity <DmaMiteReadRegs> (architecture <RTL>) with generics from library <work>.

Elaborating entity <NiFpgaFifoCountControl> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaComponent.vhd" Line 90: Net <bDataOutFromFifo[23]> does not have a driver.

Elaborating entity <MiteDmaComponent> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteDmaComponentEnableChain> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaComponentEnableChain.vhd" Line 221. Case statement is complete. others clause is never selected

Elaborating entity <MiteDmaInput> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaMiteReadInterface> (architecture <RTL>) with generics from library <work>.

Elaborating entity <NiFpgaFifo> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SyncFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopUnsigned> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopGray> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaDualPortRAM> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaDualPortRAM_Inferred> (architecture <rtl>) with generics from library <work>.

Elaborating entity <FifoReadAdapter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DmaMiteReadRegs> (architecture <RTL>) with generics from library <work>.

Elaborating entity <NiFpgaFifoCountControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteDmaComponent> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteDmaComponentEnableChain> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteDmaComponentEnableChain.vhd" Line 221. Case statement is complete. others clause is never selected

Elaborating entity <NiFpgaFifoClearControl> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoClearControl.vhd" Line 229. Case statement is complete. others clause is never selected

Elaborating entity <NiFpgaFifoPortReset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteDmaOutput> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaMiteWriteInterface> (architecture <RTL>) with generics from library <work>.

Elaborating entity <FifoWriteAdapter> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoWriteAdapter.vhd" Line 93: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoWriteAdapter.vhd" Line 119: Range is empty (null range)
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\FifoWriteAdapter.vhd" Line 179: Net <StallDisableBlk.cStallDisableLoc> does not have a driver.

Elaborating entity <NiFpgaFifo> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SyncFifoFlags> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopUnsigned> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopGray> (architecture <rtl>) with generics from library <work>.

Elaborating entity <GenDataValid> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopBoolVec> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSLV> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaDualPortRAM> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaDualPortRAM_Inferred> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CpuDataWr> (architecture <rtl>) from library <work>.

Elaborating entity <DmaMiteWriteRegs> (architecture <RTL>) with generics from library <work>.

Elaborating entity <NiFpgaFifoPopBuffer> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:92 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaFifoPopBuffer.vhd" Line 209: cpendingpushes should be on the sensitivity list of the process

Elaborating entity <NiFpgaFlipFlopFifo> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaFifoCountControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <MiteIrq> (architecture <rtl>) from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\MiteIrq.vhd" Line 337. Case statement is complete. others clause is never selected

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 83: Net <DmaClkArray[3]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 84: Net <DmaRwEnableInArray[3]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 86: Net <DmaRwEnableOutClearArray[3]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 87: Net <DmaRwDataInArray[0][31]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 89: Net <DmaRwTimeoutArray[3][31]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 92: Net <DmaCtEnableInArray[0]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 94: Net <DmaCtEnableOutClearArray[0]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 99: Net <IrqClkArray[0]> does not have a driver.
WARNING:HDLCompiler:634 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Interface.vhd" Line 104: Net <mIpIrqVec[0]> does not have a driver.

Elaborating entity <cRio9205_SyncRes> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9403SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9264SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9403SyncResource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9220Resource> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9220ResourceCore> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9220> (architecture <rtl>) with generics from library <work>.

Elaborating entity <EnableChainSM> (architecture <rtl>) from library <work>.

Elaborating entity <Crio9223EnableChainHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9223IoHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9223HseioReadHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9223ErrorDecode> (architecture <rtl>) from library <work>.

Elaborating entity <cRioCalMultiply> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioCalMemory> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9220Initializer> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9220GetCalConst> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9220CalData> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9223SampleSerializer> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9220SampleCounter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9223SampleValidDelay> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9223ClockCrossing> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCommInt> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiPulseMask> (architecture <rtl>) from library <work>.

Elaborating entity <CrioCiPicoBeatleInit> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiCartridgeDetection> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiModeSelector> (architecture <struct>) with generics from library <work>.

Elaborating entity <CrioCiModeSelectorControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiPinConfig> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiSpiConfig> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiOutputMuxes> (architecture <struct>) with generics from library <work>.

Elaborating entity <CcMuxSLN> (architecture <RTL>) with generics from library <work>.

Elaborating entity <CcMuxSL2> (architecture <RTL>) with generics from library <work>.
WARNING:HDLCompiler:89 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CcMuxSL2.vhd" Line 46: <lut6> remains a black-box since it has no binding entity.

Elaborating entity <CrioCiSpiEngine> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CcSpiLogic> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CcSpiDitherHardcodable> (architecture <RTL>) with generics from library <work>.

Elaborating entity <CcSourceSynch> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CcSourceSynchFalling> (architecture <rtl>) from library <work>.

Elaborating entity <CrioCiEeprom> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiCartridgeIdentification> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CrioCiCartridgeIdentification.vhd" Line 146: Assignment to ccartidbusy ignored, since the identifier is never used

Elaborating entity <CrioCiInitSequence> (architecture <rtl>) from library <work>.

Elaborating entity <CrioCiCrcCheck> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioParallelCrcCore> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiHsiEngine> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CcHsInput> (architecture <RTL>) with generics from library <work>.

Elaborating entity <CcHsInputLogic> (architecture <RTL>) with generics from library <work>.

Elaborating entity <CcBarrelShifter> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioCiInputFlops> (architecture <rtl>) from library <work>.

Elaborating entity <CcInputFlop> (architecture <rtl>) from library <work>.

Elaborating entity <Crio9264Resource> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9264ResourceCore> (architecture <struct>) with generics from library <work>.

Elaborating entity <cRio9264> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStock> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockModuleId> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockModeSelector> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockSpiEngine> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockEePromRead> (architecture <rtl>) from library <work>.

Elaborating entity <cRio9264EnableChainHandler> (architecture <rtl>) from library <work>.

Elaborating entity <CrioEepromRead> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9264IoHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9264UpdateHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9264GetCalConst> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9264CalReciprocal> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9264CalData> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioCalParallelCrc> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioCalMemory> (architecture <rtl>) with generics from library <work>.

Elaborating entity <ViControl> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SafeBusCrossing> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SafeBusCrossing.vhd" Line 215. Case statement is complete. others clause is never selected

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\ViControl.vhd" Line 562. Case statement is complete. others clause is never selected

Elaborating entity <DiagramReset> (architecture <rtl>) with generics from library <work>.

Elaborating entity <SafeBusCrossing> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\SafeBusCrossing.vhd" Line 215. Case statement is complete. others clause is never selected

Elaborating entity <HandshakeBaseResetCross> (architecture <rtl>) with generics from library <work>.

Elaborating entity <DFlopSlvResetVal> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\DiagramReset.vhd" Line 670. Case statement is complete. others clause is never selected

Elaborating entity <ViSignature> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaCtrlIndRegister.vhd" Line 56: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaCtrlIndRegister.vhd" Line 57: Range is empty (null range)

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaCtrlIndRegister.vhd" Line 59: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaCtrlIndRegister.vhd" Line 60: Range is empty (null range)

Elaborating entity <NiFpgaCtrlIndRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaHostAccessibleRegister> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9403Resource> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Crio9403ResourceCore> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <cRio9403> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9403EnableChainHandler> (architecture <rtl>) from library <work>.

Elaborating entity <cRioStock> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockModuleId> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockSpiEngine> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9403CommHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9403DioHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9403LdHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9403SpiWord> (architecture <rtl>) from library <work>.

Elaborating entity <CrioEepromRead> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9211Resource> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9211ResourceCore> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9211> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9211EnableChainHandler> (architecture <rtl>) from library <work>.

Elaborating entity <cRioStock> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockModuleId> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockSpiEngine> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9211IoHandler> (architecture <rtl>) with generics from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9211IoHandler.vhd" Line 498. Case statement is complete. others clause is never selected

Elaborating entity <Crio9211GetCalConst> (architecture <rtl>) from library <work>.

Elaborating entity <cRio9211CalData> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioCalMemory> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9213Resource> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9213ResourceCore> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9213> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStock> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockModuleId> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRioStockSpiEngine> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9213EnableChainHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9213IoHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9213GetCalConst> (architecture <rtl>) from library <work>.

Elaborating entity <cRioCalMemory> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio9213FxpScaleData> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213FxpScaleData.vhd" Line 203: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213FxpScaleData.vhd" Line 206: Range is empty (null range)
WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Crio9213FxpScaleData.vhd" Line 203: Assignment ignored

Elaborating entity <cRio9213UpdateHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9205_Resource> (architecture <struct>) with generics from library <work>.

Elaborating entity <Crio9205ResourceCore> (architecture <struct>) with generics from library <work>.

Elaborating entity <cRio9205> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9205CommSm> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CrioSourceSync> (architecture <rtl>) from library <work>.

Elaborating entity <cRio9205ControlSm> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9205SetTriggers> (architecture <rtl>) from library <work>.

Elaborating entity <cRio9205SettingRegs> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9205SettingRegs> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9205IoHandler> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9205GenScanLine> (architecture <rtl>) from library <work>.
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205GenScanLine.vhd" Line 143. Case statement is complete. others clause is never selected
INFO:HDLCompiler:679 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\cRio9205GenScanLine.vhd" Line 212. Case statement is complete. others clause is never selected

Elaborating entity <cRioCalMemory> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9205GetCalConst> (architecture <rtl>) with generics from library <work>.

Elaborating entity <cRio9205CalData> (architecture <rtl>) with generics from library <work>.

Elaborating entity <Crio80MhzClkRes> (architecture <struct>) from library <work>.

Elaborating entity <IDSel_Timer> (architecture <behavioral>) with generics from library <work>.

Elaborating entity <Sleep> (architecture <behavioral>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Sleep.vhd" Line 76: Assignment to din_enable_clr ignored, since the identifier is never used
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\Sleep.vhd" Line 77: Assignment to din_enable_in ignored, since the identifier is never used

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 91: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 92: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 101: Range is empty (null range)

Elaborating entity <CustomArbForTopEnablesPortOnResTopEnablePassThru> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForTmax_ctl_5RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbSerializeAccess> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbPowerOf2> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbSerializeAccess> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbPowerOf2> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForAnsteuerung_beenden_ctl_0RHFpgaReadPortOnResbushold> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 371: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 369: Range is empty (null range)
WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 369: Assignment ignored
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 379: Range is empty (null range)
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 377: Range is empty (null range)
WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 377: Assignment ignored
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaArbiter.vhd" Line 59: Range is empty (null range)
WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\PkgNiFpgaArbiter.vhd" Line 77: Assignment ignored
WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 384: Assignment ignored
WARNING:HDLCompiler:746 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 479: Range is empty (null range)
WARNING:HDLCompiler:220 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\NiFpgaArbRW.vhd" Line 479: Assignment ignored

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbSerializeAccess> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbPowerOf2> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbForMiteIoLikePortOnResInterface> (architecture <rtl>) with generics from library <work>.
WARNING:HDLCompiler:1127 - "C:\NIFPGA\jobs\G2K2D0O_KSw9nkc\CustomArbForMiteIoLikePortOnResInterface.vhd" Line 53: Assignment to interfaceclockregportin ignored, since the identifier is never used

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <NiFpgaArbRW> (architecture <rtl>) with generics from library <work>.

Elaborating entity <CustomArbFordinPortOnResSleep> (architecture <rtl>) with generics from library <work>.

=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <toplevel_gen>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd".
    Set property "OPTIMIZE = OFF" for signal <Clk40>.
WARNING:Xst:647 - Input <mIoAddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mIoHWord_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd" line 565: Output port <mDmaReady> of the instance <window> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd" line 565: Output port <TopLevelClkOut> of the instance <window> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd" line 565: Output port <tDiagramActive> of the instance <window> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd" line 565: Output port <ReliableClkOut> of the instance <window> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd" line 565: Output port <rDiagramReset> of the instance <window> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd" line 565: Output port <aDiagramReset> of the instance <window> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd" line 565: Output port <rDerivedClockLostLockError> of the instance <window> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/toplevel_gen.vhd" line 565: Output port <aSafeToEnableGatedClks> of the instance <window> is unconnected or connected to loadless signal.
Always blocking tristate driving signal <configd<3>> is removed.
Always blocking tristate driving signal <configd<2>> is removed.
Always blocking tristate driving signal <configd<1>> is removed.
Always blocking tristate driving signal <configd<0>> is removed.
    Found 1-bit tristate buffer for signal <mIoData<31>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<30>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<29>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<28>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<27>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<26>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<25>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<24>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<23>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<22>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<21>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<20>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<19>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<18>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<17>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<16>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<15>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<14>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<13>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<12>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<11>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<10>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<9>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<8>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<7>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<6>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<5>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<4>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<3>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<2>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<1>> created at line 319
    Found 1-bit tristate buffer for signal <mIoData<0>> created at line 319
    Found 1-bit tristate buffer for signal <mIoReady> created at line 359
    Found 1-bit tristate buffer for signal <system_reset_n> created at line 563
    Summary:
	inferred  34 Tristate(s).
Unit <toplevel_gen> synthesized.

Synthesizing Unit <TheWindow>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd".
    Set property "S = TRUE" for signal <Clk40Derived2x1>.
    Set property "S = TRUE" for signal <Clk40Derived2x1Clk2XFromDCM0>.
    Set property "syn_keep = true" for signal <aBusReset>.
    Set property "syn_maxfan = 100000000" for signal <aBusReset>.
WARNING:Xst:647 - Input <temp_miso> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <STATUS> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <rBufgEn> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <aBufgEn> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <CLK90> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <CLK180> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <CLK270> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <CLK2X180> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <CLKDV> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <CLKFX> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <CLKFX180> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/thewindow.vhd" line 1246: Output port <PSDONE> of the instance <NiFpgaStockDcmInst0> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <mBusReset>.
    Found 1-bit register for signal <mBusReset_ms>.
    Found 1-bit tristate buffer for signal <local_dio00_driver> created at line 158
    Found 1-bit tristate buffer for signal <local_dio01_driver> created at line 162
    Found 1-bit tristate buffer for signal <local_dio02_driver> created at line 166
    Found 1-bit tristate buffer for signal <local_dio03_driver> created at line 170
    Found 1-bit tristate buffer for signal <local_dio04_driver> created at line 174
    Found 1-bit tristate buffer for signal <local_dio05_driver> created at line 178
    Found 1-bit tristate buffer for signal <local_dio06_driver> created at line 182
    Found 1-bit tristate buffer for signal <local_dio07_driver> created at line 186
    Found 1-bit tristate buffer for signal <local_dio08_driver> created at line 190
    Found 1-bit tristate buffer for signal <local_dio09_driver> created at line 194
    Found 1-bit tristate buffer for signal <local_dio10_driver> created at line 198
    Found 1-bit tristate buffer for signal <local_dio11_driver> created at line 202
    Found 1-bit tristate buffer for signal <local_dio12_driver> created at line 206
    Found 1-bit tristate buffer for signal <local_dio13_driver> created at line 210
    Found 1-bit tristate buffer for signal <local_dio14_driver> created at line 214
    Found 1-bit tristate buffer for signal <local_dio15_driver> created at line 218
    Found 1-bit tristate buffer for signal <local_dio16_driver> created at line 222
    Found 1-bit tristate buffer for signal <local_dio17_driver> created at line 226
    Found 1-bit tristate buffer for signal <local_dio18_driver> created at line 230
    Found 1-bit tristate buffer for signal <local_dio19_driver> created at line 234
    Found 1-bit tristate buffer for signal <local_dio20_driver> created at line 238
    Found 1-bit tristate buffer for signal <local_dio21_driver> created at line 242
    Found 1-bit tristate buffer for signal <local_dio22_driver> created at line 246
    Found 1-bit tristate buffer for signal <local_dio23_driver> created at line 250
    Found 1-bit tristate buffer for signal <local_dio24_driver> created at line 254
    Found 1-bit tristate buffer for signal <local_dio25_driver> created at line 258
    Found 1-bit tristate buffer for signal <local_dio26_driver> created at line 262
    Found 1-bit tristate buffer for signal <local_dio27_driver> created at line 266
    Found 1-bit tristate buffer for signal <local_dio28_driver> created at line 270
    Found 1-bit tristate buffer for signal <local_dio29_driver> created at line 274
    Found 1-bit tristate buffer for signal <local_dio30_driver> created at line 278
    Found 1-bit tristate buffer for signal <local_dio31_driver> created at line 282
    Found 1-bit tristate buffer for signal <local_dio32_driver> created at line 286
    Found 1-bit tristate buffer for signal <local_dio33_driver> created at line 290
    Found 1-bit tristate buffer for signal <local_dio34_driver> created at line 294
    Found 1-bit tristate buffer for signal <local_dio35_driver> created at line 298
    Found 1-bit tristate buffer for signal <local_dio36_driver> created at line 302
    Found 1-bit tristate buffer for signal <local_dio37_driver> created at line 306
    Found 1-bit tristate buffer for signal <local_dio38_driver> created at line 310
    Found 1-bit tristate buffer for signal <local_dio39_driver> created at line 314
    Found 1-bit tristate buffer for signal <local_dio40_driver> created at line 318
    Found 1-bit tristate buffer for signal <local_dio41_driver> created at line 322
    Found 1-bit tristate buffer for signal <local_dio42_driver> created at line 326
    Found 1-bit tristate buffer for signal <local_dio43_driver> created at line 330
    Found 1-bit tristate buffer for signal <local_dio44_driver> created at line 334
    Found 1-bit tristate buffer for signal <local_dio45_driver> created at line 338
    Found 1-bit tristate buffer for signal <local_dio46_driver> created at line 342
    Found 1-bit tristate buffer for signal <local_dio47_driver> created at line 346
    Found 1-bit tristate buffer for signal <local_dio48_driver> created at line 350
    Found 1-bit tristate buffer for signal <local_dio49_driver> created at line 354
    Found 1-bit tristate buffer for signal <local_dio50_driver> created at line 358
    Found 1-bit tristate buffer for signal <local_dio51_driver> created at line 362
    Found 1-bit tristate buffer for signal <local_dio52_driver> created at line 366
    Found 1-bit tristate buffer for signal <local_dio53_driver> created at line 370
    Found 1-bit tristate buffer for signal <local_dio54_driver> created at line 374
    Found 1-bit tristate buffer for signal <local_dio55_driver> created at line 378
    Found 1-bit tristate buffer for signal <local_dio56_driver> created at line 382
    Found 1-bit tristate buffer for signal <local_dio57_driver> created at line 386
    Found 1-bit tristate buffer for signal <local_dio58_driver> created at line 390
    Found 1-bit tristate buffer for signal <local_dio59_driver> created at line 394
    Found 1-bit tristate buffer for signal <local_dio60_driver> created at line 398
    Found 1-bit tristate buffer for signal <local_dio61_driver> created at line 402
    Found 1-bit tristate buffer for signal <local_dio62_driver> created at line 406
    Found 1-bit tristate buffer for signal <local_dio63_driver> created at line 410
    Found 1-bit tristate buffer for signal <local_dio64_driver> created at line 414
    Found 1-bit tristate buffer for signal <local_dio65_driver> created at line 418
    Found 1-bit tristate buffer for signal <local_dio66_driver> created at line 422
    Found 1-bit tristate buffer for signal <local_dio67_driver> created at line 426
    Found 1-bit tristate buffer for signal <local_dio68_driver> created at line 430
    Found 1-bit tristate buffer for signal <local_dio69_driver> created at line 434
    Found 1-bit tristate buffer for signal <local_dio70_driver> created at line 438
    Found 1-bit tristate buffer for signal <local_dio71_driver> created at line 442
    Found 1-bit tristate buffer for signal <local_dio72_driver> created at line 446
    Found 1-bit tristate buffer for signal <local_dio73_driver> created at line 450
    Found 1-bit tristate buffer for signal <local_dio74_driver> created at line 454
    Found 1-bit tristate buffer for signal <local_dio75_driver> created at line 458
    Found 1-bit tristate buffer for signal <local_dio76_driver> created at line 462
    Found 1-bit tristate buffer for signal <local_dio77_driver> created at line 466
    Found 1-bit tristate buffer for signal <local_dio78_driver> created at line 470
    Found 1-bit tristate buffer for signal <local_dio79_driver> created at line 474
INFO:Xst:2774 - HDL ADVISOR - KEEP, MAX_FANOUT properties attached to signal aBusReset may hinder XST clustering optimizations.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred  80 Tristate(s).
Unit <TheWindow> synthesized.

Synthesizing Unit <NiFpgaStockDcm>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgastockdcm.vhd".
    Summary:
	no macro.
Unit <NiFpgaStockDcm> synthesized.

Synthesizing Unit <NiFpgaClockManagerControl>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaclockmanagercontrol.vhd".
    Set property "syn_keep = true" for signal <aBufgEnLoc>.
    Found 5-bit register for signal <rTimerCount>.
    Found 1-bit register for signal <rRstLoc>.
    Found 1-bit register for signal <rDerivedClkValidLoc>.
    Found 3-bit register for signal <rCmState>.
INFO:Xst:1799 - State waitforbufgenassertionduration is never reached in FSM <rCmState>.
INFO:Xst:1799 - State waitforbufgendeassertionduration is never reached in FSM <rCmState>.
    Found finite state machine <FSM_0> for signal <rCmState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 11                                             |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | ReliableClk (rising_edge)                      |
    | Power Up State     | waitforclkintobecomevalid                      |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit subtractor for signal <GND_129_o_GND_129_o_sub_18_OUT<4:0>> created at line 352.
    Found 1-bit 3-to-1 multiplexer for signal <rDerivedClkValidAssert> created at line 261.
    Found 1-bit 3-to-1 multiplexer for signal <rDerivedClkValidDeassert> created at line 261.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   7 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <NiFpgaClockManagerControl> synthesized.

Synthesizing Unit <DoubleSyncBoolAsyncIn_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/doublesyncboolasyncin.vhd".
    Summary:
	no macro.
Unit <DoubleSyncBoolAsyncIn_1> synthesized.

Synthesizing Unit <DoubleSyncSlAsyncIn>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/doublesyncslasyncin.vhd".
    Summary:
	no macro.
Unit <DoubleSyncSlAsyncIn> synthesized.

Synthesizing Unit <DoubleSyncAsyncInBase>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/doublesyncasyncinbase.vhd".
    Set property "syn_maxfan = 1000000" for signal <oSig_ms>.
    Set property "syn_keep = true" for signal <oSig_ms>.
    Summary:
	no macro.
Unit <DoubleSyncAsyncInBase> synthesized.

Synthesizing Unit <DFlop_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflop.vhd".
WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.
    Set property "use_clock_enable = yes" for signal <cQ>.
    Summary:
	no macro.
Unit <DFlop_1> synthesized.

Synthesizing Unit <DFlopBool_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopbool.vhd".
    Set property "syn_preserve = true".
    Summary:
	no macro.
Unit <DFlopBool_1> synthesized.

Synthesizing Unit <NiFpgaAG_Speichern4_dash_2FPGA>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1331: Output port <loopinit> of the instance <n_whileloop> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1837: Output port <cDataOut> of the instance <n_Control> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1865: Output port <clkReadData14ToReshold> of the instance <Crio9220SyncResource101> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1865: Output port <clkReadData15ToReshold> of the instance <Crio9220SyncResource101> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo0ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo1ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo2ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo3ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo4ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo5ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo6ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo7ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo8ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo9ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo11ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo12ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo13ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo14ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1928: Output port <clkAo15ToReshold> of the instance <Crio9264SyncResource102> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo0ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo1ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo2ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo3ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo4ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo5ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo6ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo7ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo8ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo9ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo11ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo12ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo13ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo14ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 1987: Output port <clkAo15ToReshold> of the instance <Crio9264SyncResource103> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo0to0ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo1to1ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo2to2ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo3to3ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo4to4ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo5to5ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo6to6ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo7to7ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo8to8ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo15to15ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo16to16ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo17to17ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo18to18ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo19to19ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo20to20ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo21to21ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo22to22ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo23to23ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo24to24ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo25to25ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo26to26ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo27to27ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo28to28ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo29to29ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo30to30ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo31to31ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo7to0ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo15to8ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo23to16ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo31to24ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDo31to0ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi0to0ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi1to1ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi2to2ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi3to3ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi4to4ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi5to5ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi6to6ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi7to7ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi8to8ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi9to9ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi10to10ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi11to11ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi12to12ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi13to13ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi14to14ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi15to15ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi16to16ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi17to17ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi18to18ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi19to19ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi20to20ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi21to21ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi22to22ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi23to23ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi24to24ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi25to25ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi26to26ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi27to27ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi28to28ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi29to29ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi30to30ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi31to31ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi7to0ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi15to8ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi23to16ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi31to24ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2284: Output port <clkDi31to0ToReshold> of the instance <Crio9403SyncResource104> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo0to0ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo1to1ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo8to8ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo9to9ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo10to10ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo11to11ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo12to12ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo13to13ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo14to14ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo15to15ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo16to16ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo17to17ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo18to18ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo19to19ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo20to20ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo21to21ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo22to22ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo23to23ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo24to24ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo25to25ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo26to26ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo27to27ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo28to28ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo29to29ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo30to30ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo31to31ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo7to0ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo15to8ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo23to16ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo31to24ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDo31to0ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi0to0ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi1to1ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi2to2ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi3to3ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi4to4ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi5to5ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi6to6ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi7to7ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi8to8ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi9to9ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi10to10ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi11to11ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi12to12ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi13to13ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi14to14ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi15to15ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi16to16ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi17to17ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi18to18ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi19to19ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi20to20ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi21to21ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi22to22ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi23to23ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi24to24ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi25to25ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi26to26ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi27to27ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi28to28ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi29to29ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi30to30ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi31to31ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi7to0ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi15to8ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi23to16ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi31to24ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2449: Output port <clkDi31to0ToReshold> of the instance <Crio9403SyncResource105> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2614: Output port <clkAi2ToReshold> of the instance <Crio9211SyncResource106> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2614: Output port <clkAi3ToReshold> of the instance <Crio9211SyncResource106> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi18ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi19ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi20ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi21ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi22ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi23ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi24ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi25ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi26ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi27ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi28ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi29ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi30ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2722: Output port <clkAi31ToReshold> of the instance <Crio9213SyncResource109> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi4toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi6toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi7toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi8toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi9toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi10toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi11toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi12toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi13toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi15toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi19toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi20toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi21toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi22toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi23toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi24toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi25toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi26toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi27toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi28toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi29toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi30toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkAi31toReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkDiChannel0ToReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2857: Output port <clkDoChannel0ToReshold> of the instance <cRio9205_SyncRes110> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2944: Output port <clkReadData14ToReshold> of the instance <Crio9220SyncResource111> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2944: Output port <clkReadData15ToReshold> of the instance <Crio9220SyncResource111> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo0to0ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo1to1ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo2to2ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo3to3ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo4to4ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo5to5ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo6to6ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo7to7ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo9to9ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo10to10ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo11to11ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo12to12ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo13to13ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo14to14ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo16to16ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo17to17ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo18to18ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo19to19ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo20to20ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo21to21ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo22to22ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo23to23ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo24to24ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo25to25ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo26to26ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo27to27ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo28to28ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo29to29ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo30to30ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo31to31ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo7to0ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo15to8ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo23to16ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo31to24ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDo31to0ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi2to2ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi3to3ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi4to4ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi5to5ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi6to6ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi7to7ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi8to8ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi9to9ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi10to10ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi11to11ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi12to12ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi13to13ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi14to14ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi15to15ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi16to16ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi17to17ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi18to18ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi19to19ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi20to20ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi21to21ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi22to22ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi23to23ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi24to24ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi25to25ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi26to26ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi27to27ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi28to28ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi29to29ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi30to30ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi31to31ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi7to0ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi15to8ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi23to16ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi31to24ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 2993: Output port <clkDi31to0ToReshold> of the instance <Crio9403SyncResource112> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo4ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo5ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo6ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo7ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo8ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo9ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo10ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo11ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo12ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo13ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo14ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3158: Output port <clkAo15ToReshold> of the instance <Crio9264SyncResource113> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo0to0ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo1to1ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo2to2ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo3to3ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo4to4ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo5to5ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo6to6ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo9to9ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo10to10ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo11to11ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo12to12ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo13to13ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo16to16ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo17to17ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo18to18ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo19to19ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo20to20ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo21to21ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo22to22ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo23to23ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo24to24ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo25to25ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo26to26ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo27to27ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo28to28ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo29to29ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo30to30ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo31to31ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo7to0ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo15to8ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo23to16ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo31to24ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDo31to0ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi0to0ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi1to1ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi2to2ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi3to3ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi4to4ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi5to5ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi6to6ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi7to7ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi8to8ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi9to9ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi10to10ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi11to11ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi12to12ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi13to13ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi14to14ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi15to15ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi16to16ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi17to17ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi18to18ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi19to19ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi20to20ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi21to21ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi22to22ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi23to23ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi24to24ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi25to25ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi26to26ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi27to27ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi28to28ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi29to29ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi30to30ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi31to31ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi7to0ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi15to8ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi23to16ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi31to24ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3217: Output port <clkDi31to0ToReshold> of the instance <Crio9403SyncResource114> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo4ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo5ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo6ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo7ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo8ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo9ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo10ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo11ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo12ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo13ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo14ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3382: Output port <clkAo15ToReshold> of the instance <Crio9264SyncResource115> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkEepromToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData0ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData1ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData2ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData3ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData4ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData5ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData6ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData7ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData8ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData9ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData10ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData11ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData12ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData13ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData14ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkReadData15ToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkHseioSamplePulsePortToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkHseioReadPortToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkHseioReadStatusPortToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkHseioResetPortToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkHseioReadyForSamplePulseToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkHseioReadyForReadToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3441: Output port <clkHseioResetInProgressToReshold> of the instance <Crio9220Resource4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3550: Output port <clkEepromToReshold> of the instance <Crio9264Resource6> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3702: Output port <rDataValueOut> of the instance <Ansteuerung_beenden_ctl_0> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3735: Output port <rDataValueOut> of the instance <Status_Quelle_ind_1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3768: Output port <rDataValueOut> of the instance <Fehler_FPGA_ind_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3801: Output port <rDataValueOut> of the instance <DCberlauf_FIFO_Daten_ind_3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3834: Output port <rDataValueOut> of the instance <DCberlauf_FIFO_Temp_ind_4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3867: Output port <rDataValueOut> of the instance <DCberschreitung_Zellgrenzwerte_ind_6> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3900: Output port <rDataValueOut> of the instance <FIFO_Ausgang_leer_ind_7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3933: Output port <rDataValueOut> of the instance <Reset_ind_8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3966: Output port <rDataValueOut> of the instance <Daten_Temperatur_ind_9> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 3999: Output port <rDataValueOut> of the instance <Zellspanunng_ind_10> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4032: Output port <rDataValueOut> of the instance <Daten_ind_11> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4065: Output port <rDataValueOut> of the instance <Tmax_ctl_5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4098: Output port <clkSetOutputDataMethodDataToReshold> of the instance <Crio9403Resource3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4098: Output port <clkLineDirectionMethodDataToReshold> of the instance <Crio9403Resource3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4098: Output port <clkEepromToReshold> of the instance <Crio9403Resource3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4156: Output port <clkEepromToReshold> of the instance <Crio9211Resource8> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4212: Output port <clkEepromToReshold> of the instance <Crio9211Resource7> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4268: Output port <clkEepromToReshold> of the instance <Crio9211Resource2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4324: Output port <clkMethodPropPortOutToReshold> of the instance <Crio9213Resource1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4324: Output port <clkConfigReadbackToReshold> of the instance <Crio9213Resource1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4324: Output port <clkEepromToReshold> of the instance <Crio9213Resource1> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkTrigToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkTerminalModePortToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkVoltageRangePortToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkInputRangePortToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkTriggersPortToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkScanLinePortToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkScanDataPortToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkRequestToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkReleaseToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkEepromToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_speichern4_dash_2fpga.vhd" line 4393: Output port <clkEeWriteToReshold> of the instance <cRio9205_Resource5> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaAG_Speichern4_dash_2FPGA> synthesized.

Synthesizing Unit <NiFpgaAG_00000000_WhileLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000000_whileloop.vhd".
WARNING:Xst:647 - Input <iteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000039<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000039<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_8000003b<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_8000003b<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_8000003d<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_8000003d<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000000_whileloop.vhd" line 297: Output port <ctrlind_00_Index> of the instance <n_SubVI_subMaxArray_vi_5937> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <res_8000003a> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <res_8000003c> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <res_8000003e> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <res_80000040> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	inferred   1 Multiplexer(s).
Unit <NiFpgaAG_00000000_WhileLoop> synthesized.

Synthesizing Unit <NiFpgaAG_00000001_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000001_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_00000001_SequenceFrame> synthesized.

Synthesizing Unit <Crio9223IoNodeResHolder>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9223ionoderesholder.vhd".
WARNING:Xst:647 - Input <error_in<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <Crio9223IoNodeResHolder> synthesized.

Synthesizing Unit <NiFpgaMergeErrors_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd" line 119: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	inferred  14 Multiplexer(s).
Unit <NiFpgaMergeErrors_1> synthesized.

Synthesizing Unit <NiLvFxpEnableHandlerSlv_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpenablehandlerslv.vhd".
    Found 1-bit register for signal <cOverflow>.
    Found 1-bit register for signal <cEnableOut>.
    Found 33-bit register for signal <cOut>.
    Summary:
	inferred  35 D-type flip-flop(s).
Unit <NiLvFxpEnableHandlerSlv_1> synthesized.

Synthesizing Unit <subMaxArray_vi_colon_Clone0>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/submaxarray_vi_colon_clone0.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/submaxarray_vi_colon_clone0.vhd" line 159: Output port <res_wo> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/submaxarray_vi_colon_clone0.vhd" line 159: Output port <data> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/submaxarray_vi_colon_clone0.vhd" line 183: Output port <res_ro> of the instance <n_SubVICtlOrIndOpt_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/submaxarray_vi_colon_clone0.vhd" line 208: Output port <res_wo> of the instance <n_SubVICtlOrInd> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/submaxarray_vi_colon_clone0.vhd" line 208: Output port <res_ro> of the instance <n_SubVICtlOrInd> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <subMaxArray_vi_colon_Clone0> synthesized.

Synthesizing Unit <resholder_r_opt>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/resholder_r_opt.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <resholder_r_opt> synthesized.

Synthesizing Unit <NiFpgaAG_00000012_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000012_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000012_forloop.vhd" line 65: Output port <shift_out> of the instance <n_ishiftreg> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	inferred   2 Multiplexer(s).
Unit <NiFpgaAG_00000012_ForLoop> synthesized.

Synthesizing Unit <NiFpgaShiftReg_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgashiftreg.vhd".
    Found 1-bit register for signal <prevDoShift>.
    Found 32-bit register for signal <nextdata>.
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaShiftReg_1> synthesized.

Synthesizing Unit <ArrayIndexNode_27>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arrayindexnode_27.vhd".
    Found 24-bit register for signal <data_out1>.
    Found 1-bit register for signal <enable_out>.
    Found 24-bit 15-to-1 multiplexer for signal <data_outL1unclipped> created at line 33.
    Found 4-bit comparator greater for signal <idxLowerGT1> created at line 69
    Summary:
	inferred  25 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   2 Multiplexer(s).
Unit <ArrayIndexNode_27> synthesized.

Synthesizing Unit <NiLvCompare_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvcompare.vhd".
WARNING:Xst:647 - Input <cTopLevelEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiLvCompare_1> synthesized.

Synthesizing Unit <NiLvFxpCompare_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpcompare.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpcompare.vhd" line 240: Output port <cOut> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal.
    Found 26-bit subtractor for signal <n0012> created at line 1547.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <NiLvFxpCompare_1> synthesized.

Synthesizing Unit <NiLvFxpEnableHandler_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpenablehandler.vhd".
    Summary:
	no macro.
Unit <NiLvFxpEnableHandler_1> synthesized.

Synthesizing Unit <NiLvFxpEnableHandlerSlv_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpenablehandlerslv.vhd".
    Found 1-bit register for signal <cOut>.
    Found 1-bit register for signal <cOverflow>.
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <NiLvFxpEnableHandlerSlv_2> synthesized.

Synthesizing Unit <NiFpgaAG_0000002d_CaseStructure_64>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000002d_casestructure_64.vhd".
    Found 2-bit register for signal <subdiag_en>.
    Found 1-bit register for signal <binenc_muxselect>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaAG_0000002d_CaseStructure_64> synthesized.

Synthesizing Unit <NiFpgaAG_00000013_CaseStructureFrame_0000>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000013_casestructureframe_0000.vhd".
WARNING:Xst:647 - Input <casesel<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tunnel_loop_index<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <enable_clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_00000013_CaseStructureFrame_0000> synthesized.

Synthesizing Unit <NiFpgaAG_00000013_CaseStructureFrame_0001>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000013_casestructureframe_0001.vhd".
WARNING:Xst:647 - Input <casesel<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tunnel_output<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <enable_clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_00000013_CaseStructureFrame_0001> synthesized.

Synthesizing Unit <forloop_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/forloop.vhd".
    Found 32-bit register for signal <iter>.
    Found 3-bit register for signal <state>.
    Found finite state machine <FSM_1> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle_st                                        |
    | Power Up State     | idle_st                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <iter_p1> created at line 220.
    Found 32-bit comparator equal for signal <complete> created at line 113
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <forloop_1> synthesized.

Synthesizing Unit <resholder_w_opt>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/resholder_w_opt.vhd".
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <resholder_w_opt> synthesized.

Synthesizing Unit <SubVICtlOrIndOpt_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/subvictlorindopt.vhd".
WARNING:Xst:647 - Input <res_ri<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_wi<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <enable_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <SubVICtlOrIndOpt_1> synthesized.

Synthesizing Unit <SubVICtlOrIndOpt_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/subvictlorindopt.vhd".
WARNING:Xst:647 - Input <res_ri<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_wi<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <enable_in> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <SubVICtlOrIndOpt_2> synthesized.

Synthesizing Unit <SubVICtlOrInd>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/subvictlorind.vhd".
WARNING:Xst:647 - Input <res_ri<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_wi<3:33>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <init<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <cReg>.
    Found 1-bit register for signal <cPrevEnableIn>.
    Found 1-bit register for signal <cBeenWritten>.
    Found 1-bit register for signal <cWriteEnableOut>.
    WARNING:Xst:2404 -  FFs/Latches <cPrevWriteEnableIn<0:0>> (without init value) have a constant value of 0 in block <SubVICtlOrInd>.
    Summary:
	inferred  34 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <SubVICtlOrInd> synthesized.

Synthesizing Unit <subMinArray_vi>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/subminarray_vi.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/subminarray_vi.vhd" line 155: Output port <res_wo> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/subminarray_vi.vhd" line 155: Output port <data> of the instance <n_SubVICtlOrIndOpt> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/subminarray_vi.vhd" line 179: Output port <res_ro> of the instance <n_SubVICtlOrIndOpt_2> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <subMinArray_vi> synthesized.

Synthesizing Unit <NiFpgaAG_00000020_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000020_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000020_forloop.vhd" line 65: Output port <shift_out> of the instance <n_ishiftreg> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	inferred   2 Multiplexer(s).
Unit <NiFpgaAG_00000020_ForLoop> synthesized.

Synthesizing Unit <NiLvCompare_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvcompare.vhd".
WARNING:Xst:647 - Input <cTopLevelEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiLvCompare_2> synthesized.

Synthesizing Unit <NiLvFxpCompare_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpcompare.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpcompare.vhd" line 240: Output port <cOut> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal.
    Found 26-bit subtractor for signal <n0012> created at line 1547.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <NiLvFxpCompare_2> synthesized.

Synthesizing Unit <NiFpgaAG_00000021_CaseStructureFrame_0000>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000021_casestructureframe_0000.vhd".
WARNING:Xst:647 - Input <casesel<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tunnel_loop_index<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <enable_clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_00000021_CaseStructureFrame_0000> synthesized.

Synthesizing Unit <NiFpgaAG_00000021_CaseStructureFrame_0001>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000021_casestructureframe_0001.vhd".
WARNING:Xst:647 - Input <casesel<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <tunnel_output<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <enable_clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_00000021_CaseStructureFrame_0001> synthesized.

Synthesizing Unit <FloatingFeedbackGInit_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/floatingfeedbackginit.vhd".
WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <FloatingFeedbackGInit_1> synthesized.

Synthesizing Unit <FeedbackNonSctlCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/feedbacknonsctlcore.vhd".
    Found 1-bit register for signal <cIterationState>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <FeedbackNonSctlCore> synthesized.

Synthesizing Unit <NiFpgaRegisterCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaregistercore.vhd".
    Summary:
	no macro.
Unit <NiFpgaRegisterCore> synthesized.

Synthesizing Unit <NiFpgaRegisterCoreBase>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaregistercorebase.vhd".
    Found 1-bit register for signal <cRegArray<0>>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaRegisterCoreBase> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderRead_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalocalresholderread.vhd".
WARNING:Xst:647 - Input <cFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cEnableOut>.
    Found 1-bit register for signal <clockDelayedEnableIn>.
    Found 8-bit register for signal <clockDataOutInternal>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <NiFpgaLocalResHolderRead_1> synthesized.

Synthesizing Unit <NiLvCompare_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvcompare.vhd".
WARNING:Xst:647 - Input <cTopLevelEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiLvCompare_3> synthesized.

Synthesizing Unit <NiLvFxpCompare_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpcompare.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpcompare.vhd" line 240: Output port <cOut> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal.
    Found 10-bit subtractor for signal <n0012> created at line 1519.
    Summary:
	inferred   1 Adder/Subtractor(s).
Unit <NiLvFxpCompare_3> synthesized.

Synthesizing Unit <NiFpgaBoolOp>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaboolop.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaboolop.vhd" line 233: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaBoolOp> synthesized.

Synthesizing Unit <NiLvToInteger>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvtointeger.vhd".
    Summary:
	no macro.
Unit <NiLvToInteger> synthesized.

Synthesizing Unit <NiLvFxpCoerce>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpcoerce.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpcoerce.vhd" line 170: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiLvFxpCoerce> synthesized.

Synthesizing Unit <NiLvFxpEnableHandler_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpenablehandler.vhd".
    Summary:
	no macro.
Unit <NiLvFxpEnableHandler_2> synthesized.

Synthesizing Unit <NiLvFxpEnableHandlerSlv_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpenablehandlerslv.vhd".
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiLvFxpEnableHandlerSlv_3> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderWrite_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalocalresholderwrite.vhd".
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaLocalResHolderWrite_1> synthesized.

Synthesizing Unit <NiFpgaAG_0000002d_CaseStructureFrame_0000>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000002d_casestructureframe_0000.vhd".
WARNING:Xst:647 - Input <casesel<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_0000002d_CaseStructureFrame_0000> synthesized.

Synthesizing Unit <NiFpgaAG_0000002e_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000002e_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_0000002e_SequenceFrame> synthesized.

Synthesizing Unit <Crio9264IoNode>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264ionode.vhd".
WARNING:Xst:647 - Input <error_in<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <Crio9264IoNode> synthesized.

Synthesizing Unit <NiFpgaMergeErrors_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd" line 119: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	inferred   1 Multiplexer(s).
Unit <NiFpgaMergeErrors_2> synthesized.

Synthesizing Unit <NiFpgaAG_0000002d_CaseStructureFrame_0001>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000002d_casestructureframe_0001.vhd".
WARNING:Xst:647 - Input <casesel<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_0000002d_CaseStructureFrame_0001> synthesized.

Synthesizing Unit <NiFpgaAG_00000032_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000032_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_00000032_SequenceFrame> synthesized.

Synthesizing Unit <whileloop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/whileloop.vhd".
    Found 2-bit register for signal <state>.
    Found 32-bit register for signal <lp_iteration>.
    Found finite state machine <FSM_2> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 11                                             |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle_st                                        |
    | Power Up State     | idle_st                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <lp_iteration[31]_GND_493_o_add_16_OUT> created at line 201.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Finite State Machine(s).
Unit <whileloop> synthesized.

Synthesizing Unit <NiFpgaAG_00000041_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000041_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_00000041_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_00000042_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000042_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_00000042_SequenceFrame> synthesized.

Synthesizing Unit <Crio9403DoIoNode>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403doionode.vhd".
WARNING:Xst:647 - Input <error_in<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 33-bit register for signal <cErrorOut>.
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred  34 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <Crio9403DoIoNode> synthesized.

Synthesizing Unit <NiFpgaMergeErrors_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd" line 119: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	inferred   6 Multiplexer(s).
Unit <NiFpgaMergeErrors_3> synthesized.

Synthesizing Unit <NiFpgaAG_0000004b_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000004b_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_0000004b_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_00000058_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000058_sequenceframe.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000058_sequenceframe.vhd" line 581: Output port <loopinit> of the instance <n_whileloop> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000058_sequenceframe.vhd" line 729: Output port <loopinit> of the instance <n_whileloop_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000058_sequenceframe.vhd" line 833: Output port <loopinit> of the instance <n_whileloop_3> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaAG_00000058_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_00000059_WhileLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000059_whileloop.vhd".
WARNING:Xst:647 - Input <iteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_00000059_WhileLoop> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderRead_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalocalresholderread.vhd".
WARNING:Xst:647 - Input <cFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <clockDataOutInternal>.
    Found 1-bit register for signal <cEnableOut>.
    Found 1-bit register for signal <clockDelayedEnableIn>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <NiFpgaLocalResHolderRead_2> synthesized.

Synthesizing Unit <NiFpgaAG_0000005a_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000005a_sequenceframe.vhd".
WARNING:Xst:647 - Input <res_80000001<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000005a_sequenceframe.vhd" line 28: Output port <cTickCount> of the instance <n_SubVI_Loop_Timer3_1462_Diagram> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <NiFpgaAG_0000005a_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaLoopTimer>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalooptimer.vhd".
    Found 1-bit register for signal <cFirstCall>.
    Found 1-bit register for signal <cEnableOutLoc>.
    Found 1-bit register for signal <cPrevLSB>.
    Found 32-bit register for signal <cTickCount>.
    Found 32-bit register for signal <cPrevWake>.
    Found 32-bit subtractor for signal <GND_581_o_GND_581_o_sub_1_OUT<31:0>> created at line 74.
    Found 32-bit comparator lessequal for signal <n0005> created at line 74
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  67 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <NiFpgaLoopTimer> synthesized.

Synthesizing Unit <NiFpgaSimpleModuloCounter>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgasimplemodulocounter.vhd".
    Found 32-bit register for signal <cModuloCounterCount>.
    Found 16-bit register for signal <cMainCounterCount>.
    Found 32-bit adder for signal <cModuloCounterCount[31]_GND_582_o_add_1_OUT> created at line 1241.
    Found 16-bit adder for signal <cMainCounterCount[15]_GND_582_o_add_2_OUT> created at line 1241.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  48 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaSimpleModuloCounter> synthesized.

Synthesizing Unit <NiFpgaAG_0000005c_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000005c_sequenceframe.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000005c_sequenceframe.vhd" line 259: Output port <tunnel_output_2> of the instance <n_NiFpgaAG_0000005d_SequenceFrame_Diagram> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000005c_sequenceframe.vhd" line 516: Output port <zeroLoopIterations> of the instance <n_forloop> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaAG_0000005c_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_0000005d_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000005d_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_0000005d_SequenceFrame> synthesized.

Synthesizing Unit <Crio9211IoNode>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211ionode.vhd".
WARNING:Xst:647 - Input <error_in<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <Crio9211IoNode> synthesized.

Synthesizing Unit <Crio9213IoNode>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213ionode.vhd".
WARNING:Xst:647 - Input <error_in<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <Crio9213IoNode> synthesized.

Synthesizing Unit <NiFpgaMergeErrors_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd" line 119: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	inferred  34 Multiplexer(s).
Unit <NiFpgaMergeErrors_4> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderWrite_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalocalresholderwrite.vhd".
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaLocalResHolderWrite_2> synthesized.

Synthesizing Unit <NiFpgaAG_00000082_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000082_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	inferred   1 Multiplexer(s).
Unit <NiFpgaAG_00000082_ForLoop> synthesized.

Synthesizing Unit <arrayLpIndx_132>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraylpindx_132.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 816-bit register for signal <tmpAry>.
    Summary:
	inferred 816 D-type flip-flop(s).
	inferred 792 Multiplexer(s).
Unit <arrayLpIndx_132> synthesized.

Synthesizing Unit <arraycollect_136>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraycollect_136.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1089-bit register for signal <tmpOut>.
    Summary:
	inferred 1089 D-type flip-flop(s).
Unit <arraycollect_136> synthesized.

Synthesizing Unit <forloop_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/forloop.vhd".
    Found 32-bit register for signal <iter>.
    Found 3-bit register for signal <state>.
    Found finite state machine <FSM_3> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle_st                                        |
    | Power Up State     | idle_st                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <iter_p1> created at line 220.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <forloop_2> synthesized.

Synthesizing Unit <NiFpgaAG_0000008e_WhileLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000008e_whileloop.vhd".
WARNING:Xst:647 - Input <iteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_0000008e_WhileLoop> synthesized.

Synthesizing Unit <NiFpgaAG_0000008f_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000008f_sequenceframe.vhd".
WARNING:Xst:647 - Input <res_80000001<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000008f_sequenceframe.vhd" line 28: Output port <cTickCount> of the instance <n_SubVI_Loop_Timer2_1209_Diagram> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <NiFpgaAG_0000008f_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_00000091_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000091_sequenceframe.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000091_sequenceframe.vhd" line 447: Output port <zeroLoopIterations> of the instance <n_forloop> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000091_sequenceframe.vhd" line 496: Output port <zeroLoopIterations> of the instance <n_forloop_2> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000091_sequenceframe.vhd" line 545: Output port <zeroLoopIterations> of the instance <n_forloop_3> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000091_sequenceframe.vhd" line 605: Output port <zeroLoopIterations> of the instance <n_forloop_4> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000091_sequenceframe.vhd" line 668: Output port <zeroLoopIterations> of the instance <n_forloop_5> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000091_sequenceframe.vhd" line 713: Output port <zeroLoopIterations> of the instance <n_forloop_6> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000091_sequenceframe.vhd" line 758: Output port <zeroLoopIterations> of the instance <n_forloop_7> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaAG_00000091_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_00000092_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_00000092_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_00000092_SequenceFrame> synthesized.

Synthesizing Unit <cRio9205_io>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205_io.vhd".
WARNING:Xst:647 - Input <error_in<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <cRio9205_io> synthesized.

Synthesizing Unit <NiFpgaMergeErrors_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd" line 119: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	inferred  23 Multiplexer(s).
Unit <NiFpgaMergeErrors_5> synthesized.

Synthesizing Unit <NiFpgaAG_000000ac_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000ac_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_000000ac_ForLoop> synthesized.

Synthesizing Unit <arrayLpIndx_173>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraylpindx_173.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 78-bit register for signal <tmpAry>.
    Summary:
	inferred  78 D-type flip-flop(s).
	inferred  53 Multiplexer(s).
Unit <arrayLpIndx_173> synthesized.

Synthesizing Unit <NiLvToFloatingPoint_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvtofloatingpoint.vhd".
    Summary:
	no macro.
Unit <NiLvToFloatingPoint_1> synthesized.

Synthesizing Unit <NiLvFixedToFloat_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfixedtofloat.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfixedtofloat.vhd" line 230: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Found 27-bit adder for signal <GND_785_o_GND_785_o_add_2_OUT> created at line 1548.
    Found 26-bit adder for signal <n0031> created at line 1548.
    Found 7-bit subtractor for signal <GND_785_o_GND_785_o_sub_11_OUT<6:0>> created at line 2044.
    Found 12-bit subtractor for signal <GND_785_o_GND_785_o_sub_12_OUT<11:0>> created at line 2044.
    Found 14-bit subtractor for signal <n0035> created at line 1547.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred   3 Multiplexer(s).
Unit <NiLvFixedToFloat_1> synthesized.

Synthesizing Unit <FxpNormalize_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/fxpnormalize.vhd".
    Found 1-bit register for signal <cStages[3]_Valid>.
    Found 1-bit register for signal <cStages[2]_Valid>.
    Found 1-bit register for signal <cStages[1]_Valid>.
    Found 1-bit register for signal <cStages[0]_Valid>.
    Found 1-bit register for signal <cStages[4]_Valid>.
    Found 26-bit register for signal <cStages[4]_Value>.
    Found 26-bit register for signal <cStages[3]_Value>.
    Found 26-bit register for signal <cStages[2]_Value>.
    Found 26-bit register for signal <cStages[1]_Value>.
    Found 26-bit register for signal <cStages[0]_Value>.
    Summary:
	inferred 135 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <FxpNormalize_1> synthesized.

Synthesizing Unit <NiLvFxpEnableHandlerSlv_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfxpenablehandlerslv.vhd".
    Found 1-bit register for signal <cOverflow>.
    Found 1-bit register for signal <cEnableOut>.
    Found 32-bit register for signal <cOut>.
    Summary:
	inferred  34 D-type flip-flop(s).
Unit <NiLvFxpEnableHandlerSlv_4> synthesized.

Synthesizing Unit <arraycollect_175>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraycollect_175.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 64-bit register for signal <tmpOut>.
    Summary:
	inferred  64 D-type flip-flop(s).
Unit <arraycollect_175> synthesized.

Synthesizing Unit <forloop_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/forloop.vhd".
    Found 32-bit register for signal <iter>.
    Found 3-bit register for signal <state>.
    Found finite state machine <FSM_4> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle_st                                        |
    | Power Up State     | idle_st                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <iter_p1> created at line 220.
    Found 32-bit comparator equal for signal <iter_p1[31]_l_max[31]_equal_4_o> created at line 123
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <forloop_3> synthesized.

Synthesizing Unit <NiFpgaAG_000000b0_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000b0_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_000000b0_ForLoop> synthesized.

Synthesizing Unit <NiFpgaAG_000000b4_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000b4_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_000000b4_ForLoop> synthesized.

Synthesizing Unit <NiFpgaAG_000000b8_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000b8_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_000000b8_ForLoop> synthesized.

Synthesizing Unit <arrayLpIndx_185>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraylpindx_185.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 336-bit register for signal <tmpAry>.
    Summary:
	inferred 336 D-type flip-flop(s).
	inferred 312 Multiplexer(s).
Unit <arrayLpIndx_185> synthesized.

Synthesizing Unit <NiLvToFloatingPoint_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvtofloatingpoint.vhd".
    Summary:
	no macro.
Unit <NiLvToFloatingPoint_2> synthesized.

Synthesizing Unit <NiLvFixedToFloat_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfixedtofloat.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfixedtofloat.vhd" line 230: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Found 25-bit adder for signal <GND_976_o_GND_976_o_add_2_OUT> created at line 1548.
    Found 8-bit subtractor for signal <GND_976_o_GND_976_o_sub_8_OUT<7:0>> created at line 2044.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred   2 Multiplexer(s).
Unit <NiLvFixedToFloat_2> synthesized.

Synthesizing Unit <FxpNormalize_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/fxpnormalize.vhd".
    Found 1-bit register for signal <cStages[3]_Valid>.
    Found 1-bit register for signal <cStages[2]_Valid>.
    Found 1-bit register for signal <cStages[1]_Valid>.
    Found 1-bit register for signal <cStages[0]_Valid>.
    Found 1-bit register for signal <cStages[4]_Valid>.
    Found 24-bit register for signal <cStages[4]_Value>.
    Found 24-bit register for signal <cStages[3]_Value>.
    Found 24-bit register for signal <cStages[2]_Value>.
    Found 24-bit register for signal <cStages[1]_Value>.
    Found 24-bit register for signal <cStages[0]_Value>.
    Summary:
	inferred 125 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <FxpNormalize_2> synthesized.

Synthesizing Unit <arraycollect_187>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraycollect_187.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 416-bit register for signal <tmpOut>.
    Summary:
	inferred 416 D-type flip-flop(s).
Unit <arraycollect_187> synthesized.

Synthesizing Unit <forloop_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/forloop.vhd".
    Found 32-bit register for signal <iter>.
    Found 3-bit register for signal <state>.
    Found finite state machine <FSM_5> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle_st                                        |
    | Power Up State     | idle_st                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <iter_p1> created at line 220.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <forloop_4> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderWrite_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalocalresholderwrite.vhd".
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaLocalResHolderWrite_3> synthesized.

Synthesizing Unit <NiFpgaAG_000000bc_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000bc_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <NiFpgaAG_000000bc_ForLoop> synthesized.

Synthesizing Unit <arrayLpIndx_189>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraylpindx_189.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 96-bit register for signal <tmpAry>.
    Summary:
	inferred  96 D-type flip-flop(s).
	inferred  65 Multiplexer(s).
Unit <arrayLpIndx_189> synthesized.

Synthesizing Unit <NiLvMultiply>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvmultiply.vhd".
    Summary:
	no macro.
Unit <NiLvMultiply> synthesized.

Synthesizing Unit <NiLvFloatMultiply>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfloatmultiply.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfloatmultiply.vhd" line 270: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiLvFloatMultiply> synthesized.

Synthesizing Unit <NiLvToFloatingPoint_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvtofloatingpoint.vhd".
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiLvToFloatingPoint_3> synthesized.

Synthesizing Unit <NiLvFloatMultiplyCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfloatmultiplycore.vhd".
    Summary:
	no macro.
Unit <NiLvFloatMultiplyCore> synthesized.

Synthesizing Unit <NiLvCoerce_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvcoerce.vhd".
    Summary:
	no macro.
Unit <NiLvCoerce_1> synthesized.

Synthesizing Unit <NiLvToFloatingPoint_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvtofloatingpoint.vhd".
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiLvToFloatingPoint_4> synthesized.

Synthesizing Unit <NiFpgaAG_000000c0_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000c0_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <NiFpgaAG_000000c0_ForLoop> synthesized.

Synthesizing Unit <NiFpgaAG_000000c4_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000c4_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <NiFpgaAG_000000c4_ForLoop> synthesized.

Synthesizing Unit <NiLvDivide>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvdivide.vhd".
    Summary:
	no macro.
Unit <NiLvDivide> synthesized.

Synthesizing Unit <NiLvFloatDivide>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfloatdivide.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfloatdivide.vhd" line 226: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfloatdivide.vhd" line 301: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvy> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiLvFloatDivide> synthesized.

Synthesizing Unit <NiLvFloatDivideCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvfloatdividecore.vhd".
    Summary:
	no macro.
Unit <NiLvFloatDivideCore> synthesized.

Synthesizing Unit <NiLvCoerce_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvcoerce.vhd".
    Summary:
	no macro.
Unit <NiLvCoerce_2> synthesized.

Synthesizing Unit <NiLvToFloatingPoint_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nilvtofloatingpoint.vhd".
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cEnableOutClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiLvToFloatingPoint_5> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderWrite_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalocalresholderwrite.vhd".
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaLocalResHolderWrite_4> synthesized.

Synthesizing Unit <NiFpgaAG_000000c8_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000c8_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	inferred   2 Multiplexer(s).
Unit <NiFpgaAG_000000c8_ForLoop> synthesized.

Synthesizing Unit <arrayLpIndx_202>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraylpindx_202.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 736-bit register for signal <tmpAry>.
    Summary:
	inferred 736 D-type flip-flop(s).
	inferred 704 Multiplexer(s).
Unit <arrayLpIndx_202> synthesized.

Synthesizing Unit <forloop_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/forloop.vhd".
    Found 32-bit register for signal <iter>.
    Found 3-bit register for signal <state>.
    Found finite state machine <FSM_6> for signal <state>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 6                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle_st                                        |
    | Power Up State     | idle_st                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <iter_p1> created at line 220.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <forloop_5> synthesized.

Synthesizing Unit <NiFpgaBoolOpNot>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaboolopnot.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaboolopnot.vhd" line 143: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaBoolOpNot> synthesized.

Synthesizing Unit <NiFpgaAG_000000de_WhileLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000de_whileloop.vhd".
WARNING:Xst:647 - Input <iteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaAG_000000de_WhileLoop> synthesized.

Synthesizing Unit <NiFpgaAG_000000df_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000df_sequenceframe.vhd".
WARNING:Xst:647 - Input <res_80000001<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <res_80000001<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000df_sequenceframe.vhd" line 30: Output port <cTickCount> of the instance <n_SubVI_Loop_Timer_43_Diagram> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <NiFpgaAG_000000df_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_000000e1_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000e1_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_000000e1_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_000000e2_ForLoop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000e2_forloop.vhd".
WARNING:Xst:647 - Input <max<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000e2_forloop.vhd" line 61: Output port <shift_out> of the instance <n_ishiftreg> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <res_80000002> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	inferred   3 Multiplexer(s).
Unit <NiFpgaAG_000000e2_ForLoop> synthesized.

Synthesizing Unit <NiFpgaShiftReg_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgashiftreg.vhd".
    Found 1-bit register for signal <prevDoShift>.
    Found 33-bit register for signal <nextdata>.
    Summary:
	inferred  34 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaShiftReg_2> synthesized.

Synthesizing Unit <FloatingFeedbackGInit_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/floatingfeedbackginit.vhd".
WARNING:Xst:647 - Input <cFromResTopEnablePassThruTopEnables<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <FloatingFeedbackGInit_2> synthesized.

Synthesizing Unit <arraycollect_232>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arraycollect_232.vhd".
WARNING:Xst:647 - Input <lpiteration<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 60-bit register for signal <tmpOut>.
    Summary:
	inferred  60 D-type flip-flop(s).
Unit <arraycollect_232> synthesized.

Synthesizing Unit <ArrayIndexNode_246>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/arrayindexnode_246.vhd".
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <enable_clr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <ArrayIndexNode_246> synthesized.

Synthesizing Unit <NiFpgaAG_000000e9_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000e9_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_000000e9_SequenceFrame> synthesized.

Synthesizing Unit <Crio9403DiIoNode>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403diionode.vhd".
WARNING:Xst:647 - Input <error_in<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <FromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 33-bit register for signal <cErrorOut>.
    Found 1-bit register for signal <cResDiDataLatched>.
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred  35 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <Crio9403DiIoNode> synthesized.

Synthesizing Unit <NiFpgaMergeErrors_6>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd" line 119: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	inferred   8 Multiplexer(s).
Unit <NiFpgaMergeErrors_6> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderWrite_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalocalresholderwrite.vhd".
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaLocalResHolderWrite_5> synthesized.

Synthesizing Unit <NiFpgaMergeErrors_7>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamergeerrors.vhd" line 119: Output port <cOverflow> of the instance <NiLvFxpEnableHandlerSlvx> is unconnected or connected to loadless signal.
    Summary:
	inferred  35 Multiplexer(s).
Unit <NiFpgaMergeErrors_7> synthesized.

Synthesizing Unit <NiFpgaAG_000000fb_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_000000fb_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_000000fb_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaAG_0000010d_SequenceFrame>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaag_0000010d_sequenceframe.vhd".
    Summary:
	no macro.
Unit <NiFpgaAG_0000010d_SequenceFrame> synthesized.

Synthesizing Unit <NiFpgaLocalResHolderWrite_6>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgalocalresholderwrite.vhd".
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaLocalResHolderWrite_6> synthesized.

Synthesizing Unit <InvisibleResholder>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/invisibleresholder.vhd".
WARNING:Xst:647 - Input <FromResbusholddummy<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <ToResbusholddummy> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <InvisibleResholder> synthesized.

Synthesizing Unit <Crio9220SyncResource>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220syncresource.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResIoNodeRelease<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResIoNodeData<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <Crio9220SyncResource> synthesized.

Synthesizing Unit <Crio9220SyncResourceLogic>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220syncresourcelogic.vhd".
    Found 1-bit register for signal <cResourceIoNodeRequestEnableIn>.
    Found 1-bit register for signal <cResourceIoNodeRequestEnableClr>.
    Found 1-bit register for signal <cResourceIoNodeRelease>.
    Found 1-bit register for signal <cResHolderEnableOut>.
    Found 33-bit register for signal <cResHolderErrorOut>.
    Found 384-bit register for signal <cResHolderReadDataInt>.
    Found 3-bit register for signal <cState>.
    Found finite state machine <FSM_7> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 11                                             |
    | Inputs             | 6                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforresholderenablein                       |
    | Power Up State     | waitforresholderenablein                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred 421 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9220SyncResourceLogic> synthesized.

Synthesizing Unit <TopEnablePassThru>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/topenablepassthru.vhd".
WARNING:Xst:647 - Input <clkTopEnablesFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <TopEnablePassThru> synthesized.

Synthesizing Unit <Crio9264SyncResource_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264syncresource.vhd".
    Set property "syn_keep = true" for signal <cIsLastChannel>.
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAoDataPort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAoDataDonePort<13:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAoDataDonePort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResRelease<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResUpdate<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResUpdateStatus<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit register for signal <cState>.
    Found 2-bit register for signal <clkToResRequest>.
    Found 5-bit register for signal <cActiveChan>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 1-bit register for signal <clkToResAoDataPort<29>>.
    Found 1-bit register for signal <clkToResAoDataPort<28>>.
    Found 1-bit register for signal <clkToResAoDataPort<27>>.
    Found 1-bit register for signal <clkToResAoDataPort<26>>.
    Found 1-bit register for signal <clkToResAoDataPort<25>>.
    Found 1-bit register for signal <clkToResAoDataPort<24>>.
    Found 1-bit register for signal <clkToResAoDataPort<23>>.
    Found 1-bit register for signal <clkToResAoDataPort<22>>.
    Found 1-bit register for signal <clkToResAoDataPort<21>>.
    Found 1-bit register for signal <clkToResAoDataPort<20>>.
    Found 1-bit register for signal <clkToResAoDataPort<19>>.
    Found 1-bit register for signal <clkToResAoDataPort<18>>.
    Found 1-bit register for signal <clkToResAoDataPort<17>>.
    Found 1-bit register for signal <clkToResAoDataPort<16>>.
    Found 1-bit register for signal <clkToResAoDataPort<15>>.
    Found 1-bit register for signal <clkToResAoDataPort<14>>.
    Found 1-bit register for signal <clkToResAoDataPort<13>>.
    Found 1-bit register for signal <clkToResAoDataPort<12>>.
    Found 1-bit register for signal <clkToResAoDataPort<11>>.
    Found 1-bit register for signal <clkToResAoDataPort<10>>.
    Found 1-bit register for signal <clkToResAoDataPort<9>>.
    Found 1-bit register for signal <clkToResAoDataPort<6>>.
    Found 1-bit register for signal <clkToResAoDataPort<5>>.
    Found 1-bit register for signal <clkToResAoDataPort<4>>.
    Found 1-bit register for signal <clkToResAoDataPort<3>>.
    Found 1-bit register for signal <clkToResAoDataPort<2>>.
    Found 1-bit register for signal <clkToResUpdate<2>>.
    Found 1-bit register for signal <clkToResRelease<2>>.
    Found 1-bit register for signal <cEnableOutSM>.
    Found 1-bit register for signal <cCleared>.
    Found 1-bit register for signal <cEnableOutInt>.
    Found finite state machine <FSM_8> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 15                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_9> for signal <clkToResRequest>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 24                                             |
    | Inputs             | 7                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit adder for signal <cActiveChan[4]_GND_1584_o_add_51_OUT> created at line 1241.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoDataEnableIn[15]_Mux_44_o> created at line 445.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<19>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<18>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<17>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<16>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<15>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<14>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<13>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<12>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<11>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<10>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<9>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<8>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<7>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<6>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<5>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<4>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<3>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<2>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<1>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<0>> created at line 441.
    WARNING:Xst:2404 -  FFs/Latches <cAoErrorOut<32:0>> (without init value) have a constant value of 0 in block <Crio9264SyncResource_1>.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  69 D-type flip-flop(s).
	inferred  91 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <Crio9264SyncResource_1> synthesized.

Synthesizing Unit <bushold>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/bushold.vhd".
WARNING:Xst:647 - Input <dummyFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResAnsteuerung_beenden_ctl_0HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResStatus_Quelle_ind_1HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResFehler_FPGA_ind_2HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResDCberlauf_FIFO_Daten_ind_3HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResDCberlauf_FIFO_Temp_ind_4HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResDCberschreitung_Zellgrenzwerte_ind_6HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResFIFO_Ausgang_leer_ind_7HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResReset_ind_8HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResDaten_Temperatur_ind_9HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResZellspanunng_ind_10HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResDaten_ind_11HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FromResTmax_ctl_5HostWrite<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/bushold.vhd" line 403: Output port <iStoredData> of the instance <Clk40Crossing.Clk40FromInterface> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/bushold.vhd" line 419: Output port <iStoredData> of the instance <Clk40Crossing.Clk40ToInterface> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/bushold.vhd" line 419: Output port <iReady> of the instance <Clk40Crossing.Clk40ToInterface> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/bushold.vhd" line 419: Output port <iOResetStatus> of the instance <Clk40Crossing.Clk40ToInterface> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/bushold.vhd" line 809: Output port <cRegDataOut> of the instance <MiteClkShifter.ShiftRegister> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/bushold.vhd" line 809: Output port <cRegWrite> of the instance <MiteClkShifter.ShiftRegister> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <dummyToReshold> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <miteClkToResViControlHostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <miteClkToResViControlHostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <miteClkToResDiagramResetHostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <miteClkToResDiagramResetHostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <miteClkToResViSignatureHostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResAnsteuerung_beenden_ctl_0HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResAnsteuerung_beenden_ctl_0HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResStatus_Quelle_ind_1HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResStatus_Quelle_ind_1HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResFehler_FPGA_ind_2HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResFehler_FPGA_ind_2HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDCberlauf_FIFO_Daten_ind_3HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDCberlauf_FIFO_Daten_ind_3HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDCberlauf_FIFO_Temp_ind_4HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDCberlauf_FIFO_Temp_ind_4HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDCberschreitung_Zellgrenzwerte_ind_6HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDCberschreitung_Zellgrenzwerte_ind_6HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResFIFO_Ausgang_leer_ind_7HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResFIFO_Ausgang_leer_ind_7HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResReset_ind_8HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResReset_ind_8HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDaten_Temperatur_ind_9HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDaten_Temperatur_ind_9HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResZellspanunng_ind_10HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResZellspanunng_ind_10HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDaten_ind_11HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResDaten_ind_11HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResTmax_ctl_5HostRead<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clk40ToResTmax_ctl_5HostWrite<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 13-bit comparator lessequal for signal <n0010> created at line 375
    Found 13-bit comparator greater for signal <iRegPortInClk40_Address[12]_GND_2276_o_LessThan_11_o> created at line 377
    Summary:
	inferred   2 Comparator(s).
	inferred  41 Multiplexer(s).
Unit <bushold> synthesized.

Synthesizing Unit <HandshakeBaseResetCross_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd".
    Set property "syn_keep = true" for signal <iPush>.
    Set property "syn_keep = true" for signal <iDlyPush>.
    Set property "syn_keep = true" for signal <iLclReady>.
    Set property "use_clock_enable = yes" for signal <oPushToggleToReady>.
    Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>.
    Set property "syn_keep = true" for signal <BlkOut.oDataAckClkEnable>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_direct_enable". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.
WARNING:Xst:647 - Input <aResetToDlyPush<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResetToIResetFast<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aPushToggleDly<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd" line 382: Output port <c1ResetFast> of the instance <BlkOut.SyncOReset> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <BlkRdy.iRdyPushToggle>.
    Found 1-bit register for signal <iLclReady>.
    Found 1-bit register for signal <iDlyPush>.
    Found 1-bit register for signal <BlkOut.oPushToggle1>.
    Found 1-bit register for signal <BlkOut.oPushToggle2>.
    Found 1-bit register for signal <oDataValid>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <HandshakeBaseResetCross_1> synthesized.

Synthesizing Unit <DFlopSlvResetVal_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopslvresetval.vhd".
    Summary:
	no macro.
Unit <DFlopSlvResetVal_1> synthesized.

Synthesizing Unit <ResetSync_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/resetsync.vhd".
    Set property "equivalent_register_removal = no".
    Found 1-bit register for signal <c1ResetFromOClk_ms>.
    Found 1-bit register for signal <c1ResetFromOClk>.
    Found 1-bit register for signal <c2ResetLcl>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <ResetSync_1> synthesized.

Synthesizing Unit <DFlopBool_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopbool.vhd".
    Set property "syn_preserve = true".
    Summary:
	no macro.
Unit <DFlopBool_2> synthesized.

Synthesizing Unit <DFlop_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflop.vhd".
WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.
    Set property "use_clock_enable = yes" for signal <cQ>.
    Summary:
	no macro.
Unit <DFlop_2> synthesized.

Synthesizing Unit <DFlopBoolFallingEdge>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopboolfallingedge.vhd".
    Set property "syn_preserve = true".
    Summary:
	no macro.
Unit <DFlopBoolFallingEdge> synthesized.

Synthesizing Unit <DFlopFallingEdge>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopfallingedge.vhd".
WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "direct_enable". This constraint/property is not supported by the current software release and will be ignored.
    Set property "use_clock_enable = yes" for signal <cQ>.
    Summary:
	no macro.
Unit <DFlopFallingEdge> synthesized.

Synthesizing Unit <ResetSync_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/resetsync.vhd".
    Set property "equivalent_register_removal = no".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/resetsync.vhd" line 86: Output port <cQ> of the instance <c2ResetFe_msx> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <c1ResetFromOClk_ms>.
    Found 1-bit register for signal <c1ResetFromOClk>.
    Found 1-bit register for signal <c2ResetLcl>.
    Found 1-bit register for signal <c2ResetRe_ms>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <ResetSync_2> synthesized.

Synthesizing Unit <HandshakeBaseResetCross_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd".
    Set property "syn_keep = true" for signal <iPush>.
    Set property "syn_keep = true" for signal <iDlyPush>.
    Set property "syn_keep = true" for signal <iLclReady>.
    Set property "use_clock_enable = yes" for signal <oPushToggleToReady>.
    Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>.
    Set property "syn_keep = true" for signal <BlkOut.oDataAckClkEnable>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_direct_enable". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.
WARNING:Xst:647 - Input <aResetToDlyPush<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResetToIResetFast<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aPushToggleDly<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd" line 382: Output port <c1ResetFast> of the instance <BlkOut.SyncOReset> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <BlkRdy.iRdyPushToggle>.
    Found 1-bit register for signal <iLclReady>.
    Found 1-bit register for signal <iDlyPush>.
    Found 1-bit register for signal <BlkOut.oPushToggle1>.
    Found 1-bit register for signal <BlkOut.oPushToggle2>.
    Found 1-bit register for signal <oDataValid>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <HandshakeBaseResetCross_2> synthesized.

Synthesizing Unit <DFlopSlvResetVal_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopslvresetval.vhd".
    Summary:
	no macro.
Unit <DFlopSlvResetVal_2> synthesized.

Synthesizing Unit <NiFpgaRegFrameworkShiftReg_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaregframeworkshiftreg.vhd".
    Found 1-bit register for signal <ReadBlk.cRegReadLoc>.
    Found 1-bit register for signal <WriteBlk.cDelayedWritePulse1>.
    Found 1-bit register for signal <WriteBlk.cDelayedWritePulse2>.
    Found 1-bit register for signal <cReadShift>.
    Found 800-bit register for signal <cShiftReg>.
    Found 5-bit register for signal <cCounter>.
    Found 5-bit subtractor for signal <GND_2481_o_GND_2481_o_sub_5_OUT<4:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 809 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
Unit <NiFpgaRegFrameworkShiftReg_1> synthesized.

Synthesizing Unit <DoubleSyncBoolAsyncIn>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/doublesyncboolasyncin.vhd".
    Summary:
	no macro.
Unit <DoubleSyncBoolAsyncIn> synthesized.

Synthesizing Unit <PulseSyncBool>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/pulsesyncbool.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/pulsesyncbool.vhd" line 58: Output port <iStatusOfoSig> of the instance <PulseSyncBasex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/pulsesyncbool.vhd" line 58: Output port <oSig> of the instance <PulseSyncBasex> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <PulseSyncBool> synthesized.

Synthesizing Unit <PulseSyncBase>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/pulsesyncbase.vhd".
    Set property "syn_maxfan = 1000000" for signal <iSigOut_ms>.
    Set property "syn_maxfan = 1000000" for signal <oHoldSigIn_ms>.
    Summary:
	no macro.
Unit <PulseSyncBase> synthesized.

Synthesizing Unit <NiFpgaRegFrameworkShiftReg_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaregframeworkshiftreg.vhd".
    Found 1-bit register for signal <ReadBlk.cRegReadLoc>.
    Found 1-bit register for signal <WriteBlk.cDelayedWritePulse1>.
    Found 1-bit register for signal <WriteBlk.cDelayedWritePulse2>.
    Found 1-bit register for signal <cReadShift>.
    Found 96-bit register for signal <cShiftReg>.
    Found 3-bit register for signal <cCounter>.
    Found 3-bit subtractor for signal <GND_2485_o_GND_2485_o_sub_5_OUT<2:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 103 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <NiFpgaRegFrameworkShiftReg_2> synthesized.

Synthesizing Unit <Crio9403SyncResource_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403syncresource.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo0to0FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo1to1FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo2to2FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo3to3FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo4to4FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo5to5FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo6to6FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo7to7FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo8to8FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo15to15FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo16to16FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo17to17FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo18to18FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo19to19FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo20to20FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo21to21FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo22to22FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo23to23FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo24to24FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo25to25FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo26to26FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo27to27FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo28to28FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo29to29FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo30to30FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to31FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo7to0FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo15to8FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo23to16FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to24FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to0FromReshold<2:33>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResDiPort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <cDiPortDataReg>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred  66 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <Crio9403SyncResource_1> synthesized.

Synthesizing Unit <Crio9403SyncResource_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403syncresource.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo0to0FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo1to1FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo8to8FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo9to9FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo10to10FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo11to11FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo12to12FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo13to13FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo14to14FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo15to15FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo16to16FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo17to17FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo18to18FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo19to19FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo20to20FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo21to21FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo22to22FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo23to23FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo24to24FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo25to25FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo26to26FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo27to27FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo28to28FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo29to29FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo30to30FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to31FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo7to0FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo15to8FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo23to16FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to24FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to0FromReshold<2:33>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResDiPort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <cDiPortDataReg>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred  66 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <Crio9403SyncResource_2> synthesized.

Synthesizing Unit <Crio9211SyncResource_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211syncresource.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi2FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi3FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAiData<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 24-bit register for signal <cInputDataArray<4>>.
    Found 24-bit register for signal <cInputDataArray<3>>.
    Found 24-bit register for signal <cInputDataArray<2>>.
    Found 24-bit register for signal <cInputDataArray<1>>.
    Found 24-bit register for signal <cInputDataArray<0>>.
    Found 24-bit register for signal <cInputDataArray<5>>.
    Found 1-bit register for signal <cEnableOutInt>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 3 bit to 8 bit decoder compact to one-hot for signal <n0163> created at line 263
    Summary:
	inferred 178 D-type flip-flop(s).
	inferred  15 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <Crio9211SyncResource_1> synthesized.

Synthesizing Unit <Crio9211SyncResource_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211syncresource.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAiData<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 24-bit register for signal <cInputDataArray<4>>.
    Found 24-bit register for signal <cInputDataArray<3>>.
    Found 24-bit register for signal <cInputDataArray<2>>.
    Found 24-bit register for signal <cInputDataArray<1>>.
    Found 24-bit register for signal <cInputDataArray<0>>.
    Found 24-bit register for signal <cInputDataArray<5>>.
    Found 1-bit register for signal <cEnableOutInt>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 3 bit to 8 bit decoder compact to one-hot for signal <n0167> created at line 263
    Summary:
	inferred 178 D-type flip-flop(s).
	inferred  15 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <Crio9211SyncResource_2> synthesized.

Synthesizing Unit <Crio9213SyncResource>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213syncresource.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResDataOutPort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResDataInPort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResRelease<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResMethodPropPortIn<33:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<31>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<30>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<29>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<28>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<27>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<26>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<25>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<24>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<23>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<22>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<21>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<20>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
WARNING:Xst:2935 - Signal 'cAiChannelDataInt<19>', unconnected in block 'Crio9213SyncResource', is tied to its initial value (000000000000000000000000).
    Found 2-bit register for signal <cState>.
    Found 2-bit register for signal <clkToResRequest>.
    Found 24-bit register for signal <cAiChannelData<18>>.
    Found 24-bit register for signal <cAiChannelData<17>>.
    Found 24-bit register for signal <cAiChannelData<16>>.
    Found 24-bit register for signal <cAiChannelData<15>>.
    Found 24-bit register for signal <cAiChannelData<14>>.
    Found 24-bit register for signal <cAiChannelData<13>>.
    Found 24-bit register for signal <cAiChannelData<12>>.
    Found 24-bit register for signal <cAiChannelData<11>>.
    Found 24-bit register for signal <cAiChannelData<10>>.
    Found 24-bit register for signal <cAiChannelData<9>>.
    Found 24-bit register for signal <cAiChannelData<8>>.
    Found 24-bit register for signal <cAiChannelData<7>>.
    Found 24-bit register for signal <cAiChannelData<6>>.
    Found 24-bit register for signal <cAiChannelData<5>>.
    Found 24-bit register for signal <cAiChannelData<4>>.
    Found 24-bit register for signal <cAiChannelData<3>>.
    Found 24-bit register for signal <cAiChannelData<2>>.
    Found 24-bit register for signal <cAiChannelData<1>>.
    Found 24-bit register for signal <cAiChannelData<0>>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 1-bit register for signal <clkToResDataOutPort<27>>.
    Found 1-bit register for signal <clkToResDataOutPort<26>>.
    Found 1-bit register for signal <clkToResDataOutPort<25>>.
    Found 1-bit register for signal <clkToResDataOutPort<24>>.
    Found 1-bit register for signal <clkToResDataOutPort<23>>.
    Found 1-bit register for signal <clkToResDataOutPort<22>>.
    Found 1-bit register for signal <clkToResDataOutPort<21>>.
    Found 1-bit register for signal <clkToResDataOutPort<20>>.
    Found 1-bit register for signal <clkToResDataOutPort<19>>.
    Found 1-bit register for signal <clkToResDataOutPort<18>>.
    Found 1-bit register for signal <clkToResDataOutPort<17>>.
    Found 1-bit register for signal <clkToResDataOutPort<16>>.
    Found 1-bit register for signal <clkToResDataOutPort<15>>.
    Found 1-bit register for signal <clkToResDataOutPort<14>>.
    Found 1-bit register for signal <clkToResDataOutPort<13>>.
    Found 1-bit register for signal <clkToResDataOutPort<12>>.
    Found 1-bit register for signal <clkToResDataOutPort<11>>.
    Found 1-bit register for signal <clkToResDataOutPort<10>>.
    Found 1-bit register for signal <clkToResDataOutPort<9>>.
    Found 1-bit register for signal <clkToResDataOutPort<8>>.
    Found 1-bit register for signal <clkToResDataOutPort<7>>.
    Found 1-bit register for signal <clkToResDataOutPort<6>>.
    Found 1-bit register for signal <clkToResDataOutPort<5>>.
    Found 1-bit register for signal <clkToResDataOutPort<4>>.
    Found 1-bit register for signal <clkToResDataOutPort<3>>.
    Found 1-bit register for signal <clkToResDataOutPort<2>>.
    Found 1-bit register for signal <clkToResRelease<2>>.
    Found 1-bit register for signal <cEnableOutSM>.
    Found 1-bit register for signal <cCleared>.
    Found 1-bit register for signal <cEnableOutInt>.
    Found finite state machine <FSM_10> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 11                                             |
    | Inputs             | 7                                              |
    | Outputs            | 21                                             |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_11> for signal <clkToResRequest>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 20                                             |
    | Inputs             | 7                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5 bit to 32 bit decoder compact to one-hot for signal <n0593> created at line 619
    Summary:
	inferred 512 D-type flip-flop(s).
	inferred  63 Multiplexer(s).
	inferred   1 Decoder(s).
	inferred   2 Finite State Machine(s).
Unit <Crio9213SyncResource> synthesized.

Synthesizing Unit <Interface>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd".
WARNING:Xst:647 - Input <clk40FIFOwTempWritePortFromReshold<3:57>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FIFOwDatenWritePortFromReshold<3:65>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk40FIFOwAusgangReadPortFromReshold<3:33>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaRwDataOutArray<0>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaRwDataOutArray<1>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaRwDataOutArray<3>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaRwCountArray<0>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaRwCountArray<1>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaRwCountArray<2>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaRwCountArray<3>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaCtEnableOutArray> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaCtCountArray<0>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaCtCountArray<1>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaCtCountArray<2>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <DmaCtCountArray<3>> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <bIrqStatusInArray[0]_Status> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <mIrq> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <bIrqInArray[0]_EnableOut> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/interface.vhd" line 157: Output port <bIrqStatusInArray[0]_EnableOut> of the instance <MiteInterfacex> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <DmaClkArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaRwEnableInArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaRwEnableOutClearArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaRwDataInArray<0><31:24>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaRwDataInArray<2>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaRwDataInArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaRwTimeoutArray<3>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaCtEnableInArray> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaCtEnableOutClearArray> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <IrqClkArray> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mIpIrqVec> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <mDmaReady> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <Interface> synthesized.

Synthesizing Unit <MiteInterface>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/miteinterface.vhd".
WARNING:Xst:647 - Input <DmaClkArray<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DmaRwEnableInArray<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DmaRwEnableOutClearArray<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DmaRwDataInArray<0><31:24>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DmaRwDataInArray<2><31:20>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DmaRwDataInArray<3><31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DmaRwTimeoutArray<3><31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DmaCtEnableInArray<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <DmaCtEnableOutClearArray<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mDmaAck_n<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <DmaCtCountArray<0><13:9>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <DmaCtCountArray<2><13:11>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <DmaBlk.mDtackOE>.
    Found 1-bit register for signal <DmaBlk.mDtack>.
    Found 32-bit register for signal <mIoDataOut>.
    Found 1-bit tristate buffer for signal <mIoDtack_n> created at line 613
    Summary:
	inferred  34 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Tristate(s).
Unit <MiteInterface> synthesized.

Synthesizing Unit <MiteInterfaceOutputEnables>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/miteinterfaceoutputenables.vhd".
    Found 1-bit register for signal <mDataOE>.
    Found 1-bit register for signal <mIoReadyOE>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <MiteInterfaceOutputEnables> synthesized.

Synthesizing Unit <RegisterAccess>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/registeraccess.vhd".
WARNING:Xst:647 - Input <mDmaAccess> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 15-bit register for signal <mIoAddrDly>.
    Found 32-bit register for signal <mIoDataInDly>.
    Summary:
	inferred  47 D-type flip-flop(s).
Unit <RegisterAccess> synthesized.

Synthesizing Unit <RegisterAccess32>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/registeraccess32.vhd".
WARNING:Xst:647 - Input <mIoAddr<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <mWriteIoReady>.
    Found 1-bit register for signal <mReadIoReady>.
    Found 1-bit register for signal <mRegPortIn_Rd>.
    Found 1-bit register for signal <mRegPortIn_Wt>.
    Found 32-bit register for signal <RegisterBlk.mIoDataOutReg>.
    Found 2-bit register for signal <WriteBlk.mWriteState>.
    Found 2-bit register for signal <ReadBlk.mReadState>.
    Found 16-bit register for signal <TimeoutManager.mCount>.
    Found finite state machine <FSM_12> for signal <WriteBlk.mWriteState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 7                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aMiteReset (positive)                          |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_13> for signal <ReadBlk.mReadState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 3                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aMiteReset (positive)                          |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 16-bit adder for signal <TimeoutManager.mCount[15]_GND_2999_o_add_17_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  52 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <RegisterAccess32> synthesized.

Synthesizing Unit <MiteDmaComponent_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponent.vhd".
WARNING:Xst:647 - Input <mIoDataIn<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mIoWt_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponent.vhd" line 123: Output port <pDisable> of the instance <EnableChains> is unconnected or connected to loadless signal.
WARNING:Xst:2935 - Signal 'bDataOutFromFifo', unconnected in block 'MiteDmaComponent_1', is tied to its initial value (000000000000000000000000).
    Summary:
	no macro.
Unit <MiteDmaComponent_1> synthesized.

Synthesizing Unit <MiteDmaComponentEnableChain_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponentenablechain.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponentenablechain.vhd" line 314: Output port <oPopFromClear> of the instance <Input.FifoClearController> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <pFlag>.
    Found 1-bit register for signal <pEnableOut>.
    Found 1-bit register for signal <mEnableOutDly>.
    Found 1-bit register for signal <pEnableInDly>.
    Found 2-bit register for signal <pTimeoutState>.
    Found 24-bit register for signal <pDataOutLoc>.
    Found finite state machine <FSM_14> for signal <pTimeoutState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 7                                              |
    | Inputs             | 4                                              |
    | Outputs            | 1                                              |
    | Clock              | PClk (rising_edge)                             |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   4 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <MiteDmaComponentEnableChain_1> synthesized.

Synthesizing Unit <TimeoutManager>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/timeoutmanager.vhd".
    Found 32-bit register for signal <cCounter>.
    Found 32-bit subtractor for signal <GND_3003_o_GND_3003_o_sub_1_OUT<31:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <TimeoutManager> synthesized.

Synthesizing Unit <NiFpgaFifoClearControl_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifoclearcontrol.vhd".
WARNING:Xst:647 - Input <oEmpty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iEmpty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cDisable>.
    Found 1-bit register for signal <cEnableOutLoc>.
    Found 1-bit register for signal <ClearRequestNoSCL.cDelayedEnableIn>.
    Found 3-bit register for signal <cDisablerState>.
    Found finite state machine <FSM_15> for signal <cDisablerState>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 18                                             |
    | Inputs             | 6                                              |
    | Outputs            | 9                                              |
    | Clock              | CClk (rising_edge)                             |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    WARNING:Xst:2404 -  FFs/Latches <oPopFromClear<0:0>> (without init value) have a constant value of 0 in block <NiFpgaFifoClearControl_1>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <NiFpgaFifoClearControl_1> synthesized.

Synthesizing Unit <DoubleSyncBool>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/doublesyncbool.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/doublesyncbool.vhd" line 58: Output port <iSigOut> of the instance <DoubleSyncBasex> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <DoubleSyncBool> synthesized.

Synthesizing Unit <DoubleSyncBase>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/doublesyncbase.vhd".
    Set property "KEEP_HIERARCHY = TRUE".
    Set property "syn_keep = true" for signal <iDlySig>.
    Summary:
	no macro.
Unit <DoubleSyncBase> synthesized.

Synthesizing Unit <NiFpgaFifoPortReset_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifoportreset.vhd".
    Found 1-bit register for signal <oResetDly>.
    Found 1-bit register for signal <iResetFromPopDly>.
    Found 1-bit register for signal <iResetFromPopDlyDly>.
    Found 1-bit register for signal <oPopDoneState>.
    Found 1-bit register for signal <cPushClearDoneLocDly>.
    Found 1-bit register for signal <iResetDly>.
    Found 1-bit register for signal <iPushDoneState>.
    Found 1-bit register for signal <oResetFromPushDly>.
    Found 1-bit register for signal <oResetFromPushDlyDly>.
    Found 1-bit register for signal <cPopClearDoneLocDly>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <NiFpgaFifoPortReset_1> synthesized.

Synthesizing Unit <NiFpgaPulseSyncBaseWrapper>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgapulsesyncbasewrapper.vhd".
    Found 1-bit register for signal <oRegisteredSigAck>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <NiFpgaPulseSyncBaseWrapper> synthesized.

Synthesizing Unit <MiteDmaInput_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmainput.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmainput.vhd" line 120: Output port <mAiFifoNumDataAvailable> of the instance <NiFpgaMiteReadInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmainput.vhd" line 120: Output port <mAiDmaIs32Bits> of the instance <NiFpgaMiteReadInterfacex> is unconnected or connected to loadless signal.
    Summary:
	inferred   1 Multiplexer(s).
Unit <MiteDmaInput_1> synthesized.

Synthesizing Unit <NiFpgaMiteReadInterface_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamitereadinterface.vhd".
    Found 1-bit register for signal <mFifoRequestBurstAccess>.
    Found 1-bit register for signal <mFifoStopBurstAccess>.
    Found 1-bit register for signal <mFifoRequestSingleAccess>.
    Found 32-bit comparator greater for signal <n0002> created at line 150
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <NiFpgaMiteReadInterface_1> synthesized.

Synthesizing Unit <NiFpgaFifo_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd" line 105: Output port <oDataValid> of the instance <NiFpgaFifoFlagsx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd" line 105: Output port <aError> of the instance <NiFpgaFifoFlagsx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaFifo_1> synthesized.

Synthesizing Unit <NiFpgaFifoFlags_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifoflags.vhd".
WARNING:Xst:2935 - Signal 'aError', unconnected in block 'NiFpgaFifoFlags_1', is tied to its initial value (0).
    Found 9-bit adder for signal <oReadAddUnsigned[8]_GND_3015_o_add_0_OUT> created at line 1241.
    Found 9-bit adder for signal <iWriteAddUnsigned[8]_GND_3015_o_add_3_OUT> created at line 1241.
    Found 9-bit subtractor for signal <BlkCnt.oLclFullCount> created at line 301.
    Found 9-bit subtractor for signal <GND_3015_o_GND_3015_o_sub_12_OUT<8:0>> created at line 309.
    Found 9-bit subtractor for signal <BlkCnt.iLclEmptyCount> created at line 300.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred   4 Multiplexer(s).
Unit <NiFpgaFifoFlags_1> synthesized.

Synthesizing Unit <SyncFifoFlags_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/syncfifoflags.vhd".
    Set property "syn_maxfan = 100000000" for signal <cAddrBGray_ms>.
    Set property "syn_keep = true" for signal <cAddrBGray_ms>.
    Summary:
Unit <SyncFifoFlags_1> synthesized.

Synthesizing Unit <DFlopUnsigned_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopunsigned.vhd".
    Summary:
	no macro.
Unit <DFlopUnsigned_1> synthesized.

Synthesizing Unit <DFlopGray_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopgray.vhd".
    Summary:
	no macro.
Unit <DFlopGray_1> synthesized.

Synthesizing Unit <GenDataValid_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/gendatavalid.vhd".
    Summary:
	inferred   1 Multiplexer(s).
Unit <GenDataValid_1> synthesized.

Synthesizing Unit <DFlopBoolVec_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopboolvec.vhd".
    Summary:
	no macro.
Unit <DFlopBoolVec_1> synthesized.

Synthesizing Unit <DFlopSLV_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopslv.vhd".
    Summary:
	no macro.
Unit <DFlopSLV_1> synthesized.

Synthesizing Unit <NiFpgaDualPortRAM_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgadualportram.vhd".
    Summary:
	no macro.
Unit <NiFpgaDualPortRAM_1> synthesized.

Synthesizing Unit <NiFpgaDualPortRAM_Inferred_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgadualportram_inferred.vhd".
    Set property "use_clock_enable = yes" for signal <oDlyAddr>.
    Set property "use_clock_enable = yes" for signal <oLclDataOut>.
WARNING:Xst:37 - Detected unknown constraint/property "block_ram". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_ramstyle = no_rw_check" for signal <iRAM>.
    Set property "ram_style = block" for signal <iRAM>.
WARNING:Xst:647 - Input <oReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 512x24-bit dual-port RAM <Mram_iRAM> for signal <iRAM>.
    Found 9-bit register for signal <oDlyAddr>.
    Summary:
	inferred   1 RAM(s).
	inferred   9 D-type flip-flop(s).
Unit <NiFpgaDualPortRAM_Inferred_1> synthesized.

Synthesizing Unit <FifoReadAdapter_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/fiforeadadapter.vhd".
WARNING:Xst:2935 - Signal 'StallDisableBlk.cStallDisableLoc', unconnected in block 'FifoReadAdapter_1', is tied to its initial value (0).
    Summary:
	no macro.
Unit <FifoReadAdapter_1> synthesized.

Synthesizing Unit <HandshakeBool>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebool.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebool.vhd" line 55: Output port <iStoredData> of the instance <HandshakeBasex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebool.vhd" line 55: Output port <oData> of the instance <HandshakeBasex> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <HandshakeBool> synthesized.

Synthesizing Unit <HandshakeBase>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebase.vhd".
    Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>.
    Set property "syn_maxfan = 1000000" for signal <BlkRdy.iReset_ms>.
    Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.
    Found 1-bit register for signal <BlkRdy.iReset>.
    Found 1-bit register for signal <BlkRdy.iReset_ms>.
    Found 1-bit register for signal <iPushToggle>.
    Found 1-bit register for signal <BlkOut.oPushToggle0_ms>.
    Found 1-bit register for signal <BlkOut.oPushToggle1>.
    Found 1-bit register for signal <BlkOut.oPushToggle2>.
    Found 1-bit register for signal <oDataValid>.
    Found 1-bit register for signal <oPushToggleToReady>.
    Found 1-bit register for signal <BlkRdy.iRdyPushToggle_ms>.
    Found 1-bit register for signal <BlkRdy.iRdyPushToggle>.
    Found 1-bit register for signal <iLclReady>.
    Found 1-bit register for signal <iDlyPush>.
    Found 2-bit register for signal <iLclStoredData>.
    Summary:
	inferred  12 D-type flip-flop(s).
Unit <HandshakeBase> synthesized.

Synthesizing Unit <DFlopSlvResetVal_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopslvresetval.vhd".
    Summary:
	no macro.
Unit <DFlopSlvResetVal_3> synthesized.

Synthesizing Unit <DmaDisabler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dmadisabler.vhd".
WARNING:Xst:647 - Input <mAccessFifo> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <mDmaDisabled>.
    Found 2-bit register for signal <mState>.
    Found finite state machine <FSM_16> for signal <mState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 11                                             |
    | Inputs             | 5                                              |
    | Outputs            | 2                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | disabled                                       |
    | Power Up State     | disabled                                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit 3-to-1 multiplexer for signal <mNxState> created at line 114.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <DmaDisabler> synthesized.

Synthesizing Unit <CpuDataRd>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/cpudatard.vhd".
    Found 4-bit register for signal <mState>.
    Found finite state machine <FSM_17> for signal <mState>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 19                                             |
    | Inputs             | 6                                              |
    | Outputs            | 9                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aMiteReset (positive)                          |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   6 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <CpuDataRd> synthesized.

Synthesizing Unit <DmaMiteReadRegs_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dmamitereadregs.vhd".
    Found 1-bit register for signal <mStartOfWrite>.
    Found 1-bit register for signal <ResetRegBlk.mResetReg>.
    Found 1-bit register for signal <StatusRegBlk.mOverflowReg>.
    Found 1-bit register for signal <mSampleCntRequestSingleAccess>.
    Found 1-bit register for signal <mSampleCntRequestBurstAccess>.
    Found 1-bit register for signal <mSampleCntStopBurstAccess>.
    Found 1-bit register for signal <mIoReadDly>.
    Found 1-bit register for signal <mStartOfRead>.
    Found 1-bit register for signal <mIoWriteDly>.
    Found 32-bit register for signal <SampleCntRegBlk.mSampleCount>.
    Found 2-bit register for signal <ControlRegBlk.mControlReg>.
    Found 32-bit adder for signal <SampleCntRegBlk.mSampleCount[31]_mIoDataIn[31]_add_14_OUT> created at line 394.
    Found 32-bit subtractor for signal <GND_3035_o_GND_3035_o_sub_14_OUT<31:0>> created at line 1308.
    Found 32-bit comparator greater for signal <GND_3035_o_SampleCntRegBlk.mSampleCount[31]_LessThan_20_o> created at line 407
    Found 32-bit comparator greater for signal <GND_3035_o_SampleCntRegBlk.mSampleCount[31]_LessThan_21_o> created at line 408
    Found 32-bit comparator greater for signal <SampleCntRegBlk.mSampleCount[31]_GND_3035_o_LessThan_22_o> created at line 409
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  43 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <DmaMiteReadRegs_1> synthesized.

Synthesizing Unit <NiFpgaFifoCountControl_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifocountcontrol.vhd".
    Found 1-bit register for signal <GenOthers.cEnableInReg>.
    Found 9-bit register for signal <cCountInQualReg>.
    Summary:
	inferred  10 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <NiFpgaFifoCountControl_1> synthesized.

Synthesizing Unit <MiteDmaComponent_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponent.vhd".
WARNING:Xst:647 - Input <mIoDataIn<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mIoWt_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponent.vhd" line 123: Output port <pDisable> of the instance <EnableChains> is unconnected or connected to loadless signal.
WARNING:Xst:2935 - Signal 'bDataOutFromFifo', unconnected in block 'MiteDmaComponent_2', is tied to its initial value (00000000000000000000000000000000).
    Summary:
	no macro.
Unit <MiteDmaComponent_2> synthesized.

Synthesizing Unit <MiteDmaComponentEnableChain_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponentenablechain.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponentenablechain.vhd" line 314: Output port <oPopFromClear> of the instance <Input.FifoClearController> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <pFlag>.
    Found 1-bit register for signal <pEnableOut>.
    Found 1-bit register for signal <mEnableOutDly>.
    Found 1-bit register for signal <pEnableInDly>.
    Found 2-bit register for signal <pTimeoutState>.
    Found 32-bit register for signal <pDataOutLoc>.
    Found finite state machine <FSM_18> for signal <pTimeoutState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 7                                              |
    | Inputs             | 4                                              |
    | Outputs            | 1                                              |
    | Clock              | PClk (rising_edge)                             |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   4 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <MiteDmaComponentEnableChain_2> synthesized.

Synthesizing Unit <MiteDmaInput_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmainput.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmainput.vhd" line 120: Output port <mAiFifoNumDataAvailable> of the instance <NiFpgaMiteReadInterfacex> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmainput.vhd" line 120: Output port <mAiDmaIs32Bits> of the instance <NiFpgaMiteReadInterfacex> is unconnected or connected to loadless signal.
    Summary:
	inferred   1 Multiplexer(s).
Unit <MiteDmaInput_2> synthesized.

Synthesizing Unit <NiFpgaMiteReadInterface_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamitereadinterface.vhd".
    Found 1-bit register for signal <mFifoRequestBurstAccess>.
    Found 1-bit register for signal <mFifoStopBurstAccess>.
    Found 1-bit register for signal <mFifoRequestSingleAccess>.
    Found 32-bit comparator greater for signal <n0002> created at line 150
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Comparator(s).
Unit <NiFpgaMiteReadInterface_2> synthesized.

Synthesizing Unit <NiFpgaFifo_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd" line 105: Output port <oDataValid> of the instance <NiFpgaFifoFlagsx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd" line 105: Output port <aError> of the instance <NiFpgaFifoFlagsx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaFifo_2> synthesized.

Synthesizing Unit <NiFpgaFifoFlags_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifoflags.vhd".
WARNING:Xst:2935 - Signal 'aError', unconnected in block 'NiFpgaFifoFlags_2', is tied to its initial value (0).
    Found 14-bit adder for signal <oReadAddUnsigned[13]_GND_3044_o_add_0_OUT> created at line 1241.
    Found 14-bit adder for signal <iWriteAddUnsigned[13]_GND_3044_o_add_3_OUT> created at line 1241.
    Found 14-bit subtractor for signal <BlkCnt.oLclFullCount> created at line 301.
    Found 14-bit subtractor for signal <GND_3044_o_GND_3044_o_sub_12_OUT<13:0>> created at line 309.
    Found 14-bit subtractor for signal <BlkCnt.iLclEmptyCount> created at line 300.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred   4 Multiplexer(s).
Unit <NiFpgaFifoFlags_2> synthesized.

Synthesizing Unit <SyncFifoFlags_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/syncfifoflags.vhd".
    Set property "syn_maxfan = 100000000" for signal <cAddrBGray_ms>.
    Set property "syn_keep = true" for signal <cAddrBGray_ms>.
    Summary:
Unit <SyncFifoFlags_2> synthesized.

Synthesizing Unit <DFlopUnsigned_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopunsigned.vhd".
    Summary:
	no macro.
Unit <DFlopUnsigned_2> synthesized.

Synthesizing Unit <DFlopGray_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopgray.vhd".
    Summary:
	no macro.
Unit <DFlopGray_2> synthesized.

Synthesizing Unit <NiFpgaDualPortRAM_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgadualportram.vhd".
    Summary:
	no macro.
Unit <NiFpgaDualPortRAM_2> synthesized.

Synthesizing Unit <NiFpgaDualPortRAM_Inferred_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgadualportram_inferred.vhd".
    Set property "use_clock_enable = yes" for signal <oDlyAddr>.
    Set property "use_clock_enable = yes" for signal <oLclDataOut>.
WARNING:Xst:37 - Detected unknown constraint/property "block_ram". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_ramstyle = no_rw_check" for signal <iRAM>.
    Set property "ram_style = block" for signal <iRAM>.
WARNING:Xst:647 - Input <oReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <oRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16384x32-bit dual-port RAM <Mram_iRAM> for signal <iRAM>.
    Found 14-bit register for signal <oDlyAddr>.
    Summary:
	inferred   1 RAM(s).
	inferred  14 D-type flip-flop(s).
Unit <NiFpgaDualPortRAM_Inferred_2> synthesized.

Synthesizing Unit <FifoReadAdapter_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/fiforeadadapter.vhd".
WARNING:Xst:2935 - Signal 'StallDisableBlk.cStallDisableLoc', unconnected in block 'FifoReadAdapter_2', is tied to its initial value (0).
    Summary:
	no macro.
Unit <FifoReadAdapter_2> synthesized.

Synthesizing Unit <DmaMiteReadRegs_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dmamitereadregs.vhd".
    Found 1-bit register for signal <mStartOfWrite>.
    Found 1-bit register for signal <ResetRegBlk.mResetReg>.
    Found 1-bit register for signal <StatusRegBlk.mOverflowReg>.
    Found 1-bit register for signal <mSampleCntRequestSingleAccess>.
    Found 1-bit register for signal <mSampleCntRequestBurstAccess>.
    Found 1-bit register for signal <mSampleCntStopBurstAccess>.
    Found 1-bit register for signal <mIoReadDly>.
    Found 1-bit register for signal <mStartOfRead>.
    Found 1-bit register for signal <mIoWriteDly>.
    Found 32-bit register for signal <SampleCntRegBlk.mSampleCount>.
    Found 2-bit register for signal <ControlRegBlk.mControlReg>.
    Found 32-bit adder for signal <SampleCntRegBlk.mSampleCount[31]_mIoDataIn[31]_add_14_OUT> created at line 394.
    Found 32-bit subtractor for signal <GND_3052_o_GND_3052_o_sub_14_OUT<31:0>> created at line 1308.
    Found 32-bit comparator greater for signal <GND_3052_o_SampleCntRegBlk.mSampleCount[31]_LessThan_20_o> created at line 407
    Found 32-bit comparator greater for signal <GND_3052_o_SampleCntRegBlk.mSampleCount[31]_LessThan_21_o> created at line 408
    Found 32-bit comparator greater for signal <SampleCntRegBlk.mSampleCount[31]_GND_3052_o_LessThan_22_o> created at line 409
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  43 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred   8 Multiplexer(s).
Unit <DmaMiteReadRegs_2> synthesized.

Synthesizing Unit <NiFpgaFifoCountControl_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifocountcontrol.vhd".
    Found 1-bit register for signal <GenOthers.cEnableInReg>.
    Found 14-bit register for signal <cCountInQualReg>.
    Summary:
	inferred  15 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <NiFpgaFifoCountControl_2> synthesized.

Synthesizing Unit <MiteDmaComponent_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponent.vhd".
WARNING:Xst:647 - Input <bRwDataIn<19:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <mIoRd_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <MiteDmaComponent_3> synthesized.

Synthesizing Unit <MiteDmaComponentEnableChain_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponentenablechain.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmacomponentenablechain.vhd" line 341: Output port <oPopFromClear> of the instance <Output.FifoClearController> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <pFlag>.
    Found 1-bit register for signal <pEnableOut>.
    Found 1-bit register for signal <mEnableOutDly>.
    Found 1-bit register for signal <pEnableInDly>.
    Found 2-bit register for signal <pTimeoutState>.
    Found 20-bit register for signal <pDataOutLoc>.
    Found finite state machine <FSM_19> for signal <pTimeoutState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 7                                              |
    | Inputs             | 4                                              |
    | Outputs            | 1                                              |
    | Clock              | PClk (rising_edge)                             |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  24 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <MiteDmaComponentEnableChain_3> synthesized.

Synthesizing Unit <NiFpgaFifoClearControl_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifoclearcontrol.vhd".
WARNING:Xst:647 - Input <oEmpty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <iEmpty> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:2935 - Signal 'oPopFromClear', unconnected in block 'NiFpgaFifoClearControl_2', is tied to its initial value (0).
    Found 1-bit register for signal <cDisable>.
    Found 1-bit register for signal <cEnableOutLoc>.
    Found 1-bit register for signal <ClearRequestNoSCL.cDelayedEnableIn>.
    Found 3-bit register for signal <cDisablerState>.
    Found finite state machine <FSM_20> for signal <cDisablerState>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 18                                             |
    | Inputs             | 6                                              |
    | Outputs            | 9                                              |
    | Clock              | CClk (rising_edge)                             |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <NiFpgaFifoClearControl_2> synthesized.

Synthesizing Unit <NiFpgaFifoPortReset_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifoportreset.vhd".
    Found 1-bit register for signal <oResetDly>.
    Found 1-bit register for signal <iResetFromPopDly>.
    Found 1-bit register for signal <iResetFromPopDlyDly>.
    Found 1-bit register for signal <oPopDoneState>.
    Found 1-bit register for signal <cPushClearDoneLocDly>.
    Found 1-bit register for signal <iResetDly>.
    Found 1-bit register for signal <iPushDoneState>.
    Found 1-bit register for signal <oResetFromPushDly>.
    Found 1-bit register for signal <oResetFromPushDlyDly>.
    Found 1-bit register for signal <cPopClearDoneLocDly>.
    Summary:
	inferred  10 D-type flip-flop(s).
Unit <NiFpgaFifoPortReset_2> synthesized.

Synthesizing Unit <MiteDmaOutput>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmaoutput.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/mitedmaoutput.vhd" line 164: Output port <cPopFlag> of the instance <PopBuffer> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <MiteDmaOutput> synthesized.

Synthesizing Unit <NiFpgaMiteWriteInterface>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgamitewriteinterface.vhd".
    Found 1-bit register for signal <mFifoRequestBurstAccess>.
    Found 1-bit register for signal <mFifoStopBurstAccess>.
    Found 1-bit register for signal <mFifoRequestSingleAccess>.
    Found 32-bit comparator greater for signal <n0002> created at line 229
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaMiteWriteInterface> synthesized.

Synthesizing Unit <FifoWriteAdapter>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/fifowriteadapter.vhd".
WARNING:Xst:2935 - Signal 'StallDisableBlk.cStallDisableLoc', unconnected in block 'FifoWriteAdapter', is tied to its initial value (0).
    Found 1-bit register for signal <cFlags>.
    Summary:
	no macro.
Unit <FifoWriteAdapter> synthesized.

Synthesizing Unit <NiFpgaFifo_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd" line 105: Output port <oDataValid> of the instance <NiFpgaFifoFlagsx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifo.vhd" line 105: Output port <aError> of the instance <NiFpgaFifoFlagsx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <NiFpgaFifo_3> synthesized.

Synthesizing Unit <NiFpgaFifoFlags_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifoflags.vhd".
WARNING:Xst:2935 - Signal 'aError', unconnected in block 'NiFpgaFifoFlags_3', is tied to its initial value (0).
    Found 10-bit adder for signal <oReadAddUnsigned[9]_GND_3066_o_add_0_OUT> created at line 1241.
    Found 10-bit adder for signal <iWriteAddUnsigned[9]_GND_3066_o_add_3_OUT> created at line 1241.
    Found 10-bit subtractor for signal <BlkCnt.oLclFullCount> created at line 301.
    Found 10-bit subtractor for signal <GND_3066_o_GND_3066_o_sub_12_OUT<9:0>> created at line 309.
    Found 10-bit subtractor for signal <BlkCnt.iLclEmptyCount> created at line 300.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred   4 Multiplexer(s).
Unit <NiFpgaFifoFlags_3> synthesized.

Synthesizing Unit <SyncFifoFlags_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/syncfifoflags.vhd".
    Set property "syn_maxfan = 100000000" for signal <cAddrBGray_ms>.
    Set property "syn_keep = true" for signal <cAddrBGray_ms>.
    Summary:
Unit <SyncFifoFlags_3> synthesized.

Synthesizing Unit <DFlopUnsigned_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopunsigned.vhd".
    Summary:
	no macro.
Unit <DFlopUnsigned_3> synthesized.

Synthesizing Unit <DFlopGray_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopgray.vhd".
    Summary:
	no macro.
Unit <DFlopGray_3> synthesized.

Synthesizing Unit <GenDataValid_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/gendatavalid.vhd".
    Summary:
	inferred   1 Multiplexer(s).
Unit <GenDataValid_2> synthesized.

Synthesizing Unit <DFlopBoolVec_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopboolvec.vhd".
    Summary:
	no macro.
Unit <DFlopBoolVec_2> synthesized.

Synthesizing Unit <DFlopSLV_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopslv.vhd".
    Summary:
	no macro.
Unit <DFlopSLV_2> synthesized.

Synthesizing Unit <NiFpgaDualPortRAM_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgadualportram.vhd".
    Summary:
	no macro.
Unit <NiFpgaDualPortRAM_3> synthesized.

Synthesizing Unit <NiFpgaDualPortRAM_Inferred_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgadualportram_inferred.vhd".
    Set property "use_clock_enable = yes" for signal <oDlyAddr>.
    Set property "use_clock_enable = yes" for signal <oLclDataOut>.
WARNING:Xst:37 - Detected unknown constraint/property "block_ram". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_ramstyle = no_rw_check" for signal <iRAM>.
    Set property "ram_style = block" for signal <iRAM>.
WARNING:Xst:647 - Input <oRead> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1024x20-bit dual-port RAM <Mram_iRAM> for signal <iRAM>.
    Found 20-bit register for signal <oLclDataOut>.
    Found 10-bit register for signal <oDlyAddr>.
    Summary:
	inferred   1 RAM(s).
	inferred  30 D-type flip-flop(s).
Unit <NiFpgaDualPortRAM_Inferred_3> synthesized.

Synthesizing Unit <CpuDataWr>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/cpudatawr.vhd".
    Found 1-bit register for signal <mAoWriteFifo>.
    Found 4-bit register for signal <mState>.
    Found finite state machine <FSM_21> for signal <mState>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 20                                             |
    | Inputs             | 6                                              |
    | Outputs            | 6                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aMiteReset (positive)                          |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <CpuDataWr> synthesized.

Synthesizing Unit <DmaMiteWriteRegs>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dmamitewriteregs.vhd".
    Found 1-bit register for signal <mReadDly>.
    Found 1-bit register for signal <mEndOfRead>.
    Found 1-bit register for signal <ResetRegBlk.mResetReg>.
    Found 1-bit register for signal <BlkSampleCounter.mSampleCntState>.
    Found 1-bit register for signal <mSampleCntRequestSingleAccess>.
    Found 1-bit register for signal <mSampleCntRequestBurstAccess>.
    Found 1-bit register for signal <mSampleCntStopBurstAccess>.
    Found 1-bit register for signal <mWriteDly>.
    Found 3-bit register for signal <BlkSampleCounter.mErrorState>.
    Found 32-bit register for signal <BlkSampleCounter.mAccumulator>.
    Found 32-bit register for signal <BlkSampleCounter.mSampleCount>.
    Found 5-bit register for signal <BlkSampleCounter.mDiscardCount>.
    Found 2-bit register for signal <ControlRegBlk.mControlReg>.
    Found finite state machine <FSM_22> for signal <BlkSampleCounter.mErrorState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 20                                             |
    | Inputs             | 6                                              |
    | Outputs            | 9                                              |
    | Clock              | MiteClk (rising_edge)                          |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 32-bit adder for signal <BlkSampleCounter.mAccumulator[31]_mIoDataIn[31]_add_34_OUT> created at line 621.
    Found 32-bit adder for signal <BlkSampleCounter.mSampleCount[31]_BlkSampleCounter.mAccumulator[31]_add_47_OUT> created at line 647.
    Found 32-bit subtractor for signal <GND_3076_o_GND_3076_o_sub_36_OUT<31:0>> created at line 1308.
    Found 5-bit subtractor for signal <GND_3076_o_GND_3076_o_sub_50_OUT<4:0>> created at line 1308.
    Found 3-bit 6-to-1 multiplexer for signal <BlkSampleCounter.mNxErrorState> created at line 509.
    Found 32-bit comparator greater for signal <BlkSampleCounter.mSampleCount[31]_GND_3076_o_LessThan_15_o> created at line 515
    Found 5-bit comparator greater for signal <n0090> created at line 694
    Found 32-bit comparator greater for signal <n0095> created at line 698
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  82 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred  23 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <DmaMiteWriteRegs> synthesized.

Synthesizing Unit <NiFpgaFifoPopBuffer>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifopopbuffer.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifopopbuffer.vhd" line 322: Output port <cPushFlag> of the instance <NiFpgaFlipFlopFifox> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifopopbuffer.vhd" line 322: Output port <cPopFlag> of the instance <NiFpgaFlipFlopFifox> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <FullCountBlk.cExtendedCountAvailable>.
    Found 2-bit register for signal <FullCountBlk.cPendingPushes>.
    Found 2-bit register for signal <DelayBlk.cPushes>.
    Found 3-bit register for signal <FullCountBlk.cBufferFullCountPlusPendingPushes>.
    Found 2-bit adder for signal <FullCountBlk.cPendingPushes[1]_GND_3078_o_add_5_OUT> created at line 1241.
    Found 3-bit adder for signal <cBufferFullCount[2]_GND_3078_o_add_14_OUT> created at line 1241.
    Found 3-bit adder for signal <GND_3078_o_FullCountBlk.cNxBufferFullCount[2]_add_20_OUT> created at line 265.
    Found 11-bit adder for signal <GND_3078_o_GND_3078_o_add_22_OUT> created at line 278.
    Found 2-bit subtractor for signal <GND_3078_o_GND_3078_o_sub_4_OUT<1:0>> created at line 1308.
    Found 3-bit subtractor for signal <GND_3078_o_GND_3078_o_sub_13_OUT<2:0>> created at line 1308.
    Found 10-bit comparator greater for signal <cFullCountFromFifo[9]_GND_3078_o_LessThan_1_o> created at line 125
    Found 3-bit comparator lessequal for signal <n0018> created at line 220
    Found 3-bit comparator greater for signal <GND_3078_o_FullCountBlk.cNxBufferFullCount[2]_LessThan_17_o> created at line 240
    Found 3-bit comparator greater for signal <GND_3078_o_FullCountBlk.cNxBufferFullCount[2]_LessThan_18_o> created at line 241
    Found 2-bit comparator lessequal for signal <n0034> created at line 241
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred   8 D-type flip-flop(s).
	inferred   5 Comparator(s).
	inferred   7 Multiplexer(s).
Unit <NiFpgaFifoPopBuffer> synthesized.

Synthesizing Unit <NiFpgaFlipFlopFifo>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaflipflopfifo.vhd".
WARNING:Xst:2935 - Signal 'cPushFlag', unconnected in block 'NiFpgaFlipFlopFifo', is tied to its initial value (0).
WARNING:Xst:2935 - Signal 'cPopFlag', unconnected in block 'NiFpgaFlipFlopFifo', is tied to its initial value (0).
    Found 20-bit register for signal <cFifo<5>>.
    Found 20-bit register for signal <cFifo<4>>.
    Found 20-bit register for signal <cFifo<3>>.
    Found 20-bit register for signal <cFifo<2>>.
    Found 20-bit register for signal <cFifo<1>>.
    Found 20-bit register for signal <cFifo<0>>.
    Found 3-bit register for signal <cFullCountLoc>.
    Found 3-bit register for signal <cEmptyCountLoc>.
    Found 7-bit register for signal <cFlags>.
    Found 3-bit adder for signal <cFullCountLoc[2]_GND_3079_o_add_24_OUT> created at line 1241.
    Found 3-bit adder for signal <cEmptyCountLoc[2]_GND_3079_o_add_26_OUT> created at line 1241.
    Found 3-bit subtractor for signal <GND_3079_o_GND_3079_o_sub_23_OUT<2:0>> created at line 1308.
    Found 3-bit subtractor for signal <GND_3079_o_GND_3079_o_sub_29_OUT<2:0>> created at line 1308.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 133 D-type flip-flop(s).
	inferred  10 Multiplexer(s).
Unit <NiFpgaFlipFlopFifo> synthesized.

Synthesizing Unit <NiFpgaFifoCountControl_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgafifocountcontrol.vhd".
    Found 1-bit register for signal <GenOthers.cEnableInReg>.
    Found 11-bit register for signal <cCountInQualReg>.
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <NiFpgaFifoCountControl_3> synthesized.

Synthesizing Unit <MiteIrq>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/miteirq.vhd".
WARNING:Xst:647 - Input <iIrqStatusEnableClear> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/miteirq.vhd" line 379: Output port <iStoredData> of the instance <HandShakeIrqNum> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/miteirq.vhd" line 444: Output port <iStoredData> of the instance <HandShakeIrqAck> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/miteirq.vhd" line 444: Output port <iOResetStatus> of the instance <HandShakeIrqAck> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <iPushIrqNumState>.
    Found 1-bit register for signal <iIrqEnableOut>.
    Found 1-bit register for signal <mDiagramReset>.
    Found 1-bit register for signal <mIoWriteDly>.
    Found 1-bit register for signal <mStartOfWrite>.
    Found 1-bit register for signal <mIoReadDly>.
    Found 1-bit register for signal <mStartOfRead>.
    Found 1-bit register for signal <mIeReg>.
    Found 1-bit register for signal <mStatusReg<0>>.
    Found 1-bit register for signal <mStatusReg<1>>.
    Found 1-bit register for signal <mStatusReg<2>>.
    Found 1-bit register for signal <mStatusReg<3>>.
    Found 1-bit register for signal <mStatusReg<4>>.
    Found 1-bit register for signal <mStatusReg<5>>.
    Found 1-bit register for signal <mStatusReg<6>>.
    Found 1-bit register for signal <mStatusReg<7>>.
    Found 1-bit register for signal <mStatusReg<8>>.
    Found 1-bit register for signal <mStatusReg<9>>.
    Found 1-bit register for signal <mStatusReg<10>>.
    Found 1-bit register for signal <mStatusReg<11>>.
    Found 1-bit register for signal <mStatusReg<12>>.
    Found 1-bit register for signal <mStatusReg<13>>.
    Found 1-bit register for signal <mStatusReg<14>>.
    Found 1-bit register for signal <mStatusReg<15>>.
    Found 1-bit register for signal <mStatusReg<16>>.
    Found 1-bit register for signal <mStatusReg<17>>.
    Found 1-bit register for signal <mStatusReg<18>>.
    Found 1-bit register for signal <mStatusReg<19>>.
    Found 1-bit register for signal <mStatusReg<20>>.
    Found 1-bit register for signal <mStatusReg<21>>.
    Found 1-bit register for signal <mStatusReg<22>>.
    Found 1-bit register for signal <mStatusReg<23>>.
    Found 1-bit register for signal <mStatusReg<24>>.
    Found 1-bit register for signal <mStatusReg<25>>.
    Found 1-bit register for signal <mStatusReg<26>>.
    Found 1-bit register for signal <mStatusReg<27>>.
    Found 1-bit register for signal <mStatusReg<28>>.
    Found 1-bit register for signal <mStatusReg<29>>.
    Found 1-bit register for signal <mStatusReg<30>>.
    Found 1-bit register for signal <mStatusReg<31>>.
    Found 1-bit register for signal <mIrq>.
    Found 1-bit register for signal <mDiagramReset_ms>.
    Found 32-bit register for signal <mMaskReg>.
    Summary:
	inferred  72 D-type flip-flop(s).
	inferred  37 Multiplexer(s).
Unit <MiteIrq> synthesized.

Synthesizing Unit <HandshakeBaseResetCross_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd".
    Set property "syn_keep = true" for signal <iPush>.
    Set property "syn_keep = true" for signal <iDlyPush>.
    Set property "syn_keep = true" for signal <iLclReady>.
    Set property "use_clock_enable = yes" for signal <oPushToggleToReady>.
    Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>.
    Set property "syn_keep = true" for signal <BlkOut.oDataAckClkEnable>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_direct_enable". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.
WARNING:Xst:647 - Input <aResetToDlyPush<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResetToIResetFast<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aPushToggleDly<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd" line 382: Output port <c1ResetFast> of the instance <BlkOut.SyncOReset> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <BlkRdy.iRdyPushToggle>.
    Found 1-bit register for signal <iLclReady>.
    Found 1-bit register for signal <iDlyPush>.
    Found 1-bit register for signal <BlkOut.oPushToggle1>.
    Found 1-bit register for signal <BlkOut.oPushToggle2>.
    Found 1-bit register for signal <oDataValid>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <HandshakeBaseResetCross_3> synthesized.

Synthesizing Unit <DFlopSlvResetVal_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopslvresetval.vhd".
    Summary:
	no macro.
Unit <DFlopSlvResetVal_4> synthesized.

Synthesizing Unit <cRio9205_SyncRes>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205_syncres.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAiData<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi4FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi6FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi7FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi8FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi9FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi10FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi11FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi12FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi13FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi15FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi19FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi20FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi21FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi22FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi23FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi24FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi25FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi26FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi27FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi28FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi29FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi30FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAi31FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDiChannel0FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDoChannel0FromReshold<0:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 26-bit register for signal <cAiChannelData<30>>.
    Found 26-bit register for signal <cAiChannelData<29>>.
    Found 26-bit register for signal <cAiChannelData<28>>.
    Found 26-bit register for signal <cAiChannelData<27>>.
    Found 26-bit register for signal <cAiChannelData<26>>.
    Found 26-bit register for signal <cAiChannelData<25>>.
    Found 26-bit register for signal <cAiChannelData<24>>.
    Found 26-bit register for signal <cAiChannelData<23>>.
    Found 26-bit register for signal <cAiChannelData<22>>.
    Found 26-bit register for signal <cAiChannelData<21>>.
    Found 26-bit register for signal <cAiChannelData<20>>.
    Found 26-bit register for signal <cAiChannelData<19>>.
    Found 26-bit register for signal <cAiChannelData<18>>.
    Found 26-bit register for signal <cAiChannelData<17>>.
    Found 26-bit register for signal <cAiChannelData<16>>.
    Found 26-bit register for signal <cAiChannelData<15>>.
    Found 26-bit register for signal <cAiChannelData<14>>.
    Found 26-bit register for signal <cAiChannelData<13>>.
    Found 26-bit register for signal <cAiChannelData<12>>.
    Found 26-bit register for signal <cAiChannelData<11>>.
    Found 26-bit register for signal <cAiChannelData<10>>.
    Found 26-bit register for signal <cAiChannelData<9>>.
    Found 26-bit register for signal <cAiChannelData<8>>.
    Found 26-bit register for signal <cAiChannelData<7>>.
    Found 26-bit register for signal <cAiChannelData<6>>.
    Found 26-bit register for signal <cAiChannelData<5>>.
    Found 26-bit register for signal <cAiChannelData<4>>.
    Found 26-bit register for signal <cAiChannelData<3>>.
    Found 26-bit register for signal <cAiChannelData<2>>.
    Found 26-bit register for signal <cAiChannelData<1>>.
    Found 26-bit register for signal <cAiChannelData<0>>.
    Found 26-bit register for signal <cAiChannelData<31>>.
    Found 1-bit register for signal <cDiChannel0Data>.
    Found 1-bit register for signal <cEnableOutInt>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 5 bit to 32 bit decoder compact to one-hot for signal <clkFromResAiData[5]_Decoder_33_OUT> created at line 455
    Summary:
	inferred 867 D-type flip-flop(s).
	inferred  69 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <cRio9205_SyncRes> synthesized.

Synthesizing Unit <Crio9403SyncResource_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403syncresource.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo0to0FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo1to1FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo2to2FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo3to3FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo4to4FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo5to5FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo6to6FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo7to7FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo9to9FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo10to10FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo11to11FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo12to12FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo13to13FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo14to14FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo16to16FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo17to17FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo18to18FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo19to19FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo20to20FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo21to21FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo22to22FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo23to23FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo24to24FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo25to25FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo26to26FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo27to27FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo28to28FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo29to29FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo30to30FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to31FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo7to0FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo15to8FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo23to16FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to24FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to0FromReshold<2:33>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResDiPort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <cDiPortDataReg>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred  66 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <Crio9403SyncResource_3> synthesized.

Synthesizing Unit <Crio9264SyncResource_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264syncresource.vhd".
    Set property "syn_keep = true" for signal <cIsLastChannel>.
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAoDataPort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAoDataDonePort<13:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResAoDataDonePort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResRelease<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResUpdate<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResUpdateStatus<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 3-bit register for signal <cState>.
    Found 2-bit register for signal <clkToResRequest>.
    Found 5-bit register for signal <cActiveChan>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 1-bit register for signal <clkToResAoDataPort<29>>.
    Found 1-bit register for signal <clkToResAoDataPort<28>>.
    Found 1-bit register for signal <clkToResAoDataPort<27>>.
    Found 1-bit register for signal <clkToResAoDataPort<26>>.
    Found 1-bit register for signal <clkToResAoDataPort<25>>.
    Found 1-bit register for signal <clkToResAoDataPort<24>>.
    Found 1-bit register for signal <clkToResAoDataPort<23>>.
    Found 1-bit register for signal <clkToResAoDataPort<22>>.
    Found 1-bit register for signal <clkToResAoDataPort<21>>.
    Found 1-bit register for signal <clkToResAoDataPort<20>>.
    Found 1-bit register for signal <clkToResAoDataPort<19>>.
    Found 1-bit register for signal <clkToResAoDataPort<18>>.
    Found 1-bit register for signal <clkToResAoDataPort<17>>.
    Found 1-bit register for signal <clkToResAoDataPort<16>>.
    Found 1-bit register for signal <clkToResAoDataPort<15>>.
    Found 1-bit register for signal <clkToResAoDataPort<14>>.
    Found 1-bit register for signal <clkToResAoDataPort<13>>.
    Found 1-bit register for signal <clkToResAoDataPort<12>>.
    Found 1-bit register for signal <clkToResAoDataPort<11>>.
    Found 1-bit register for signal <clkToResAoDataPort<10>>.
    Found 1-bit register for signal <clkToResAoDataPort<9>>.
    Found 1-bit register for signal <clkToResAoDataPort<6>>.
    Found 1-bit register for signal <clkToResAoDataPort<5>>.
    Found 1-bit register for signal <clkToResAoDataPort<4>>.
    Found 1-bit register for signal <clkToResAoDataPort<3>>.
    Found 1-bit register for signal <clkToResAoDataPort<2>>.
    Found 1-bit register for signal <clkToResUpdate<2>>.
    Found 1-bit register for signal <clkToResRelease<2>>.
    Found 1-bit register for signal <cEnableOutSM>.
    Found 1-bit register for signal <cCleared>.
    Found 1-bit register for signal <cEnableOutInt>.
    Found finite state machine <FSM_23> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 15                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_24> for signal <clkToResRequest>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 24                                             |
    | Inputs             | 7                                              |
    | Outputs            | 2                                              |
    | Clock              | clk (rising_edge)                              |
    | Reset              | reset (positive)                               |
    | Reset type         | asynchronous                                   |
    | Reset State        | 00                                             |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit adder for signal <cActiveChan[4]_GND_3599_o_add_51_OUT> created at line 1241.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoDataEnableIn[15]_Mux_44_o> created at line 445.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<19>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<18>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<17>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<16>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<15>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<14>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<13>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<12>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<11>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<10>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<9>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<8>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<7>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<6>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<5>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<4>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<3>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<2>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<1>> created at line 441.
    Found 1-bit 16-to-1 multiplexer for signal <cActiveChan[3]_cUsedAoChannelData[15][19]_wide_mux_45_OUT<0>> created at line 441.
    WARNING:Xst:2404 -  FFs/Latches <cAoErrorOut<32:0>> (without init value) have a constant value of 0 in block <Crio9264SyncResource_2>.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  69 D-type flip-flop(s).
	inferred  91 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <Crio9264SyncResource_2> synthesized.

Synthesizing Unit <Crio9403SyncResource_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403syncresource.vhd".
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo0to0FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo1to1FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo2to2FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo3to3FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo4to4FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo5to5FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo6to6FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo9to9FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo10to10FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo11to11FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo12to12FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo13to13FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo16to16FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo17to17FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo18to18FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo19to19FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo20to20FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo21to21FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo22to22FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo23to23FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo24to24FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo25to25FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo26to26FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo27to27FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo28to28FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo29to29FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo30to30FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to31FromReshold<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo7to0FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo15to8FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo23to16FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to24FromReshold<2:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDo31to0FromReshold<2:33>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResDiPort<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResError<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 32-bit register for signal <cDiPortDataReg>.
    Found 1-bit register for signal <clkErrorToReshold<33>>.
    Found 1-bit register for signal <clkErrorToReshold<32>>.
    Found 1-bit register for signal <clkErrorToReshold<31>>.
    Found 1-bit register for signal <clkErrorToReshold<30>>.
    Found 1-bit register for signal <clkErrorToReshold<29>>.
    Found 1-bit register for signal <clkErrorToReshold<28>>.
    Found 1-bit register for signal <clkErrorToReshold<27>>.
    Found 1-bit register for signal <clkErrorToReshold<26>>.
    Found 1-bit register for signal <clkErrorToReshold<25>>.
    Found 1-bit register for signal <clkErrorToReshold<24>>.
    Found 1-bit register for signal <clkErrorToReshold<23>>.
    Found 1-bit register for signal <clkErrorToReshold<22>>.
    Found 1-bit register for signal <clkErrorToReshold<21>>.
    Found 1-bit register for signal <clkErrorToReshold<20>>.
    Found 1-bit register for signal <clkErrorToReshold<19>>.
    Found 1-bit register for signal <clkErrorToReshold<18>>.
    Found 1-bit register for signal <clkErrorToReshold<17>>.
    Found 1-bit register for signal <clkErrorToReshold<16>>.
    Found 1-bit register for signal <clkErrorToReshold<15>>.
    Found 1-bit register for signal <clkErrorToReshold<14>>.
    Found 1-bit register for signal <clkErrorToReshold<13>>.
    Found 1-bit register for signal <clkErrorToReshold<12>>.
    Found 1-bit register for signal <clkErrorToReshold<11>>.
    Found 1-bit register for signal <clkErrorToReshold<10>>.
    Found 1-bit register for signal <clkErrorToReshold<9>>.
    Found 1-bit register for signal <clkErrorToReshold<8>>.
    Found 1-bit register for signal <clkErrorToReshold<7>>.
    Found 1-bit register for signal <clkErrorToReshold<6>>.
    Found 1-bit register for signal <clkErrorToReshold<5>>.
    Found 1-bit register for signal <clkErrorToReshold<4>>.
    Found 1-bit register for signal <clkErrorToReshold<3>>.
    Found 1-bit register for signal <clkErrorToReshold<2>>.
    Found 1-bit register for signal <clkErrorToReshold<1>>.
    Found 1-bit register for signal <cEnableOut>.
    Summary:
	inferred  66 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <Crio9403SyncResource_4> synthesized.

Synthesizing Unit <Crio9220Resource>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220resource.vhd".
    Summary:
	no macro.
Unit <Crio9220Resource> synthesized.

Synthesizing Unit <Crio9220ResourceCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220resourcecore.vhd".
WARNING:Xst:647 - Input <clkFromResdin<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResIdSelTick<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResClk80Mhz<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResClk80Mhz<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkIoNodeReleaseFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkIoNodeDataFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData0FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData1FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData2FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData3FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData4FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData5FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData6FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData7FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData8FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData9FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData10FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData11FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData12FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData13FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData14FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReadData15FromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkHseioSamplePulsePortFromReshold<0:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkHseioReadPortFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkHseioReadStatusPortFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkHseioReadyForSamplePulseFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkHseioReadyForReadFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkHseioResetInProgressFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <Crio9220ResourceCore> synthesized.

Synthesizing Unit <Crio9220>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cSpiDataIn> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInOClk> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInTrig> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInDone_n> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInConv_n> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInFunc> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInCs_n> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInMiso> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInMosi> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <aResCrioBusInSpiClk> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cResOeDone> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cModeRequestDone> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cModeReleaseDone> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cSpiDataValid> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cSpiDone> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cSpiQueued> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cSpiCommandAck> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cHsiOutputReadReq> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cHsiOutputTransferCompleteStrobe> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220.vhd" line 712: Output port <cEepromWriteTimeout> of the instance <CrioCommIntx> is unconnected or connected to loadless signal.
    Found 24-bit register for signal <cReadData1>.
    Found 24-bit register for signal <cReadData2>.
    Found 24-bit register for signal <cReadData3>.
    Found 24-bit register for signal <cReadData4>.
    Found 24-bit register for signal <cReadData5>.
    Found 24-bit register for signal <cReadData6>.
    Found 24-bit register for signal <cReadData7>.
    Found 24-bit register for signal <cReadData8>.
    Found 24-bit register for signal <cReadData9>.
    Found 24-bit register for signal <cReadData10>.
    Found 24-bit register for signal <cReadData11>.
    Found 24-bit register for signal <cReadData12>.
    Found 24-bit register for signal <cReadData13>.
    Found 24-bit register for signal <cReadData14>.
    Found 24-bit register for signal <cReadData15>.
    Found 24-bit register for signal <cReadData0>.
    Found 8-bit register for signal <fRegisteredEepromData>.
    Summary:
	inferred 392 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <Crio9220> synthesized.

Synthesizing Unit <EnableChainSM>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/enablechainsm.vhd".
    Found 1-bit register for signal <cEnableOutInt>.
    Found 1-bit register for signal <cResRunInt>.
    Found 2-bit register for signal <cState>.
    Found finite state machine <FSM_25> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 10                                             |
    | Inputs             | 3                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   1 Finite State Machine(s).
Unit <EnableChainSM> synthesized.

Synthesizing Unit <Crio9223EnableChainHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9223enablechainhandler.vhd".
    Found 1-bit register for signal <cCounter>.
    Found 1-bit register for signal <cIoNodeRequestEnableDoneInt>.
    Found 1-bit register for signal <cIoNodeRequestEnableDoneIntDly>.
    Found 1-bit register for signal <cIoNodeRequestRun>.
    Found 1-bit register for signal <cIoNodeDoneInt>.
    Found 1-bit register for signal <cEepromEnableDoneInt>.
    Found 1-bit register for signal <cEepromPropertyRun>.
    Found 1-bit register for signal <cHseioModuleReadyForSamplePulse>.
    Found 1-bit register for signal <cIoNodeRunningInt>.
    Found 1-bit register for signal <cHseioResetEnableDoneInt>.
    Found 10-bit register for signal <cEepromPropertyAddress>.
    Found 4-bit register for signal <cState>.
    Found 2-bit register for signal <cHseioSamplesOutstanding>.
    Found finite state machine <FSM_26> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 33                                             |
    | Inputs             | 16                                             |
    | Outputs            | 9                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit subtractor for signal <n0157> created at line 1308.
    Found 2-bit adder for signal <cHseioSamplesOutstanding[1]_GND_4401_o_add_19_OUT> created at line 1241.
    Found 2-bit subtractor for signal <GND_4401_o_GND_4401_o_sub_23_OUT<1:0>> created at line 1308.
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred  22 D-type flip-flop(s).
	inferred  47 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9223EnableChainHandler> synthesized.

Synthesizing Unit <Crio9223IoHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9223iohandler.vhd".
    Found 1-bit register for signal <cConv_n>.
    Found 1-bit register for signal <cIoNodeComplete>.
    Found 1-bit register for signal <cIoNodeError>.
    Found 1-bit register for signal <cIoNodeInvocation>.
    Found 1-bit register for signal <cHseioMinSampleTimeMet>.
    Found 1-bit register for signal <cIoNodeRequestDone>.
    Found 3-bit register for signal <cState>.
    Found 9-bit register for signal <cCounter>.
    Found finite state machine <FSM_27> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 18                                             |
    | Inputs             | 7                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit subtractor for signal <GND_4403_o_GND_4403_o_sub_19_OUT<8:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  15 D-type flip-flop(s).
	inferred  18 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9223IoHandler> synthesized.

Synthesizing Unit <Crio9223HseioReadHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9223hseioreadhandler.vhd".
WARNING:Xst:647 - Input <cModuleStatus<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHseioReadChannelMask<15:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHseioReadStatusStrobes<15:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cSampleDataValid> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cSampleDataError> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cIoNodeRunning> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHseioResetInProgress> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHseioGatedSamplePulse> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHseioReadStrobe> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <Crio9223HseioReadHandler> synthesized.

Synthesizing Unit <Crio9223ErrorDecode>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9223errordecode.vhd".
    Found 1-bit register for signal <cPowerupConditions>.
    Found 3-bit register for signal <cModuleStatusDelayed>.
    Found 33-bit register for signal <cError>.
    Summary:
	inferred  37 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <Crio9223ErrorDecode> synthesized.

Synthesizing Unit <cRioCalMultiply>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocalmultiply.vhd".
    Found 36-bit register for signal <cMultOutBuf>.
    Found 18x18-bit multiplier for signal <cMultIn1[17]_cMultIn2[17]_MuLt_0_OUT> created at line 75.
    Summary:
	inferred   1 Multiplier(s).
	inferred  36 D-type flip-flop(s).
Unit <cRioCalMultiply> synthesized.

Synthesizing Unit <cRioCalMemory_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocalmemory.vhd".
    Set property "ram_style = distributed" for signal <cCalMemData>.
    Found 16x35-bit single-port RAM <Mram_cCalMemData> for signal <cCalMemData>.
    Summary:
	inferred   1 RAM(s).
Unit <cRioCalMemory_1> synthesized.

Synthesizing Unit <Crio9220Initializer>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220initializer.vhd".
    Summary:
	no macro.
Unit <Crio9220Initializer> synthesized.

Synthesizing Unit <Crio9220GetCalConst>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220getcalconst.vhd".
    Found 1-bit register for signal <cCalMemWrEn>.
    Found 1-bit register for signal <cCrcError>.
    Found 1-bit register for signal <cCalMemInit>.
    Found 1-bit register for signal <cEepromRun>.
    Found 1-bit register for signal <cDone>.
    Found 3-bit register for signal <cCountCalBytes>.
    Found 6-bit register for signal <cCountCalWords>.
    Found 32-bit register for signal <cCalDataRaw>.
    Found 2-bit register for signal <cMultInSel>.
    Found 36-bit register for signal <cMultBuf>.
    Found 35-bit register for signal <cCalMemWrData>.
    Found 41-bit register for signal <cAccum>.
    Found 4-bit register for signal <cCalMemWrAddr>.
    Found 4-bit register for signal <cState>.
    Found 16-bit register for signal <cEepromAddress>.
    Found 8-bit register for signal <cEepromNumBytes>.
    Found finite state machine <FSM_28> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 26                                             |
    | Inputs             | 7                                              |
    | Outputs            | 8                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <cCountCalBytes[2]_GND_4413_o_add_3_OUT> created at line 1241.
    Found 6-bit adder for signal <cCountCalWords[5]_GND_4413_o_add_29_OUT> created at line 1241.
    Found 41-bit adder for signal <cMultBuf[22]_cAccum[39]_add_30_OUT> created at line 1548.
    Found 41-bit adder for signal <cMultBuf[5]_cAccum[39]_add_38_OUT> created at line 1548.
    Found 3-bit comparator greater for signal <cCountCalBytes[2]_PWR_474_o_LessThan_13_o> created at line 156
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred 188 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  66 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9220GetCalConst> synthesized.

Synthesizing Unit <Crio9220CalData>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220caldata.vhd".
WARNING:Xst:647 - Input <cMultOut<35:34>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cCalDataError>.
    Found 1-bit register for signal <cMultInSel>.
    Found 1-bit register for signal <cCalDataReady>.
    Found 3-bit register for signal <cState>.
    Found 37-bit register for signal <cCalibratedDataTemp>.
    Found 5-bit register for signal <cCurChannel>.
    Found 36-bit register for signal <cMultBuf>.
    Found 24-bit register for signal <cCalDataSample>.
    Found finite state machine <FSM_29> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 14                                             |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 37-bit adder for signal <cCalibratedDataTemp[5]_cMultBuf[5]_add_4_OUT> created at line 1584.
    Found 5-bit adder for signal <cCurChannel[4]_GND_4414_o_add_5_OUT> created at line 183.
    Found 37-bit subtractor for signal <cCalibratedDataTemp[5]_cOffsetBuf[-4]_sub_1_OUT<36:0>> created at line 2044.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred 105 D-type flip-flop(s).
	inferred  23 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9220CalData> synthesized.

Synthesizing Unit <Crio9223SampleSerializer>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9223sampleserializer.vhd".
    Found 1-bit register for signal <cHsiInputWriteReqDelayed>.
    Found 1-bit register for signal <cSecondRawSampleReady>.
    Found 1-bit register for signal <cSecondRawSample>.
    Found 1-bit register for signal <cCancelSampleStrobeInt>.
    Found 4-bit register for signal <cChunkCounter>.
    Found 2-bit register for signal <cState>.
    Found 3-bit register for signal <cLatencyCounter>.
    Found finite state machine <FSM_30> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 9                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforhsiinputwritereq                        |
    | Power Up State     | waitforhsiinputwritereq                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit subtractor for signal <GND_4415_o_GND_4415_o_sub_10_OUT<2:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_4415_o_GND_4415_o_sub_21_OUT<3:0>> created at line 1308.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  11 D-type flip-flop(s).
	inferred  13 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9223SampleSerializer> synthesized.

Synthesizing Unit <Crio9220SampleCounter>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9220samplecounter.vhd".
WARNING:Xst:647 - Input <cSampleData<23:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cSampleCompleteRaw>.
    Found 4-bit register for signal <cSampleCounter>.
    Found 4-bit adder for signal <cSampleCounter[3]_GND_4417_o_add_1_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   5 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
Unit <Crio9220SampleCounter> synthesized.

Synthesizing Unit <Crio9223SampleValidDelay>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9223samplevaliddelay.vhd".
    Found 1-bit register for signal <cSampleDataValid>.
    Found 1-bit register for signal <cState>.
    Found 5-bit register for signal <cCounter>.
    Found 5-bit subtractor for signal <GND_4418_o_GND_4418_o_sub_2_OUT<4:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   7 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
Unit <Crio9223SampleValidDelay> synthesized.

Synthesizing Unit <Crio9223ClockCrossing>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9223clockcrossing.vhd".
    Set property "syn_keep = true" for signal <fEepromPropertyAddressPulse>.
    Set property "S = YES" for signal <fEepromPropertyAddressPulse>.
    Set property "syn_keep = true" for signal <fEepromPropertyAddressPulseInt>.
    Set property "S = YES" for signal <fEepromPropertyAddressPulseInt>.
    Set property "syn_keep = true" for signal <cSleep>.
    Set property "S = YES" for signal <cSleep>.
    Set property "syn_keep = true" for signal <fSleep>.
    Set property "S = YES" for signal <fSleep>.
    Set property "syn_keep = true" for signal <cIdSelTimerTick>.
    Set property "S = YES" for signal <cIdSelTimerTick>.
    Set property "syn_keep = true" for signal <fIdSelTimerTickPulse>.
    Set property "S = YES" for signal <fIdSelTimerTickPulse>.
    Found 1-bit register for signal <fIdSelTimerTick>.
    Found 1-bit register for signal <fEepromPropertyRunPulseDelayed>.
    Found 1-bit register for signal <fEepromPropertyRun>.
    Found 1-bit register for signal <fEepromDoneDelayed>.
    Found 1-bit register for signal <cEepromDone>.
    Found 1-bit register for signal <fCalDataReadyDelayed>.
    Found 1-bit register for signal <cSampleDataValidRaw>.
    Found 1-bit register for signal <fIdSelTimerTickPulseDelayed>.
    Found 10-bit register for signal <fEepromPropertyAddress>.
    Summary:
	inferred  18 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <Crio9223ClockCrossing> synthesized.

Synthesizing Unit <CrioCommInt>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocommint.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocommint.vhd" line 446: Output port <cCartDetOverrideDone> of the instance <CrioCiCartridgeDetectionx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocommint.vhd" line 584: Output port <cSpiCsDone> of the instance <CrioCiSpiEnginex> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <CrioCommInt> synthesized.

Synthesizing Unit <CrioCiPulseMask>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocipulsemask.vhd".
    Found 1-bit register for signal <cMaskInt>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <CrioCiPulseMask> synthesized.

Synthesizing Unit <CrioCiPicoBeatleInit>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocipicobeatleinit.vhd".
    Found 1-bit register for signal <cPbInitDone_ms>.
    Found 1-bit register for signal <cPbInitDone>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <CrioCiPicoBeatleInit> synthesized.

Synthesizing Unit <CrioCiCartridgeDetection>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocicartridgedetection.vhd".
WARNING:Xst:647 - Input <cCartDetOverrideEnable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cCartDetOverridePresent> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cOverridingCartridgePresent>.
    Found 1-bit register for signal <cCartridgePresent>.
    Found 1-bit register for signal <cIdSel_ms>.
    Found 1-bit register for signal <cIdSel>.
    Found 1-bit register for signal <cIdSelWasRecentlyDriven>.
    Found 1-bit register for signal <cOneTickHasPassed>.
    Found 1-bit register for signal <cCartridgePresentInt>.
    Found 1-bit register for signal <cCartDetBusy>.
    Found 1-bit register for signal <cForcedCartidgePresent>.
    Found 5-bit register for signal <cCounter>.
    Found 5-bit subtractor for signal <GND_4423_o_GND_4423_o_sub_7_OUT<4:0>> created at line 1308.
    WARNING:Xst:2404 -  FFs/Latches <cCartDetOverrideDoneInt<0:0>> (without init value) have a constant value of 0 in block <CrioCiCartridgeDetection>.
    WARNING:Xst:2404 -  FFs/Latches <cCartDetOverrideDone<0:0>> (without init value) have a constant value of 0 in block <CrioCiCartridgeDetection>.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  14 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <CrioCiCartridgeDetection> synthesized.

Synthesizing Unit <CrioCiModeSelector>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocimodeselector.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocimodeselector.vhd" line 208: Output port <cSpiDivideRateOverrideDone> of the instance <CrioCiSpiConfigx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <CrioCiModeSelector> synthesized.

Synthesizing Unit <CrioCiModeSelectorControl>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocimodeselectorcontrol.vhd".
    Found 1-bit register for signal <cInitDefaultModeIsIdlePrev>.
    Found 1-bit register for signal <cPinConfRun>.
    Found 1-bit register for signal <cSpiConfRun>.
    Found 1-bit register for signal <cModeRequestDone>.
    Found 1-bit register for signal <cModeReleaseDone>.
    Found 1-bit register for signal <cHsiEnable>.
    Found 1-bit register for signal <cHsiEnableRun>.
    Found 1-bit register for signal <cDefaultModeJustChanged>.
    Found 4-bit register for signal <cState>.
    Found 2-bit register for signal <cMode>.
    Found 2-bit register for signal <cRequestedMode>.
    Found 2-bit register for signal <cCurrentDefaultMode>.
    Found finite state machine <FSM_31> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 16                                             |
    | Transitions        | 35                                             |
    | Inputs             | 7                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforwakeuporinsertion                       |
    | Power Up State     | waitforwakeuporinsertion                       |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4x2-bit Read Only RAM for signal <cMode[1]_X_427_o_wide_mux_17_OUT>
    Summary:
	inferred   1 RAM(s).
	inferred  14 D-type flip-flop(s).
	inferred  21 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <CrioCiModeSelectorControl> synthesized.

Synthesizing Unit <CrioCiPinConfig>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocipinconfig.vhd".
    Found 1-bit register for signal <cPinConfDoneInt>.
    Found 1-bit register for signal <cResOeDone>.
    Found 10-bit register for signal <cDelayCounter>.
    Found 10-bit register for signal <cCrioBusOe>.
    Found 10-bit register for signal <cPinConfConstOutInt>.
    Found 3-bit register for signal <cState>.
    Found 2-bit register for signal <cStepNumber>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<0>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<1>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<2>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<3>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<4>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<5>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<6>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<7>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<8>>.
    Found 2-bit register for signal <cPinConfSourceSelectInt<9>>.
    Found 2-bit register for signal <cCurrentMode>.
INFO:Xst:1799 - State updateoeonly is never reached in FSM <cState>.
    Found finite state machine <FSM_32> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 9                                              |
    | Inputs             | 4                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforrun                                     |
    | Power Up State     | waitforrun                                     |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit adder for signal <cStepNumber[1]_GND_4432_o_add_4283_OUT> created at line 741.
    Found 10-bit subtractor for signal <GND_4432_o_GND_4432_o_sub_4281_OUT<9:0>> created at line 1308.
    Found 4x66-bit Read Only RAM for signal <_n0889>
    Found 10-bit 3-to-1 multiplexer for signal <cTargetMode[1]_X_428_o_wide_mux_26_OUT> created at line 656.
    Found 10-bit 3-to-1 multiplexer for signal <cTargetMode[1]_X_428_o_wide_mux_27_OUT> created at line 656.
    Found 10-bit 3-to-1 multiplexer for signal <cStepNumber[1]_X_428_o_wide_mux_29_OUT> created at line 656.
    Found 1-bit 3-to-1 multiplexer for signal <cStepNumber[1]_X_428_o_wide_mux_2362_OUT<6>> created at line 0.
    Found 1-bit 3-to-1 multiplexer for signal <cStepNumber[1]_X_428_o_wide_mux_2419_OUT<5>> created at line 0.
    Found 1-bit 3-to-1 multiplexer for signal <cStepNumber[1]_X_428_o_wide_mux_2639_OUT<1>> created at line 0.
    Found 1-bit 3-to-1 multiplexer for signal <cStepNumber[1]_X_428_o_wide_mux_2696_OUT<0>> created at line 0.
    Found 1-bit 3-to-1 multiplexer for signal <cTargetMode[1]_X_428_o_wide_mux_2200_OUT[9]> created at line 290.
    Found 1-bit 3-to-1 multiplexer for signal <cTargetMode[1]_X_428_o_wide_mux_2200_OUT[4]> created at line 290.
    Found 1-bit 3-to-1 multiplexer for signal <cTargetMode[1]_X_428_o_wide_mux_2200_OUT[1]> created at line 290.
    Found 1-bit 3-to-1 multiplexer for signal <cTargetMode[1]_X_428_o_wide_mux_2202_OUT[0]> created at line 290.
    Found 1-bit 3-to-1 multiplexer for signal <cTargetMode[1]_X_428_o_wide_mux_2204_OUT[1]> created at line 290.
    Found 2-bit comparator greater for signal <GND_4432_o_cTargetMode[1]_LessThan_3816_o> created at line 117
    Found 2-bit comparator greater for signal <GND_4432_o_cTargetMode[1]_LessThan_3892_o> created at line 117
    Found 2-bit comparator greater for signal <GND_4432_o_cTargetMode[1]_LessThan_3968_o> created at line 117
    Found 2-bit comparator greater for signal <GND_4432_o_cTargetMode[1]_LessThan_4183_o> created at line 117
    Summary:
	inferred   1 RAM(s).
	inferred   2 Adder/Subtractor(s).
	inferred  45 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  73 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <CrioCiPinConfig> synthesized.

Synthesizing Unit <CrioCiSpiConfig>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocispiconfig.vhd".
WARNING:Xst:647 - Input <cSpiDivideRateOverride<19:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cSpiDivideRateOverrideEnable> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cSpiSampleRisingEdge>.
    Found 1-bit register for signal <cSpiConfDone>.
    Found 2-bit register for signal <cSpiClkSource>.
    Found 6-bit register for signal <cSpiDivideRate>.
    Found 4x6-bit Read Only RAM for signal <cSpiConfMode[1]_X_429_o_wide_mux_0_OUT>
    WARNING:Xst:2404 -  FFs/Latches <cSpiDivideRateOverrideDone<0:0>> (without init value) have a constant value of 0 in block <CrioCiSpiConfig>.
    Summary:
	inferred   1 RAM(s).
	inferred   7 D-type flip-flop(s).
Unit <CrioCiSpiConfig> synthesized.

Synthesizing Unit <CrioCiOutputMuxes>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocioutputmuxes.vhd".
WARNING:Xst:647 - Input <cPinConfSourceSelect<9><1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cPinConfConstOut<8:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiOClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiTrig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiDone_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiConv_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiFunc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiCs_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiMiso> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiMosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiSpiClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResOClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResTrig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResDone_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResFunc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResCs_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResMiso> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResMosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResSpiClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <CrioCiOutputMuxes> synthesized.

Synthesizing Unit <CcMuxSLN>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/ccmuxsln.vhd".
    Set property "syn_keep = true" for signal <aSel>.
    Set property "KEEP = TRUE" for signal <aSel>.
    Set property "syn_keep = true" for signal <Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal>.
    Set property "KEEP = TRUE" for signal <Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal>.
    Set property "syn_keep = true" for signal <aDataOut>.
    Set property "KEEP = TRUE" for signal <aDataOut>.
    Summary:
	no macro.
Unit <CcMuxSLN> synthesized.

Synthesizing Unit <CcMuxSL2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/ccmuxsl2.vhd".
    Set property "syn_hier = hard".
    Set property "KEEP_HIERARCHY = YES".
    Set property "LOCK_PINS = ALL" for instance <Lut6Mux.LUT6x>.
    Set property "syn_keep = true" for signal <aDataIn>.
    Set property "KEEP = TRUE" for signal <aDataIn>.
    Set property "syn_keep = true" for signal <aSel>.
    Set property "KEEP = TRUE" for signal <aSel>.
    Set property "syn_keep = true" for signal <aDataOut>.
    Set property "KEEP = TRUE" for signal <aDataOut>.
    Summary:
	no macro.
Unit <CcMuxSL2> synthesized.

Synthesizing Unit <CrioCiSpiEngine>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocispiengine.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocispiengine.vhd" line 310: Output port <oSpiDivideCounter> of the instance <SpiEnabled.CcSpiLogicx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocispiengine.vhd" line 310: Output port <oSpiOutputBitCounter> of the instance <SpiEnabled.CcSpiLogicx> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cContinueCommand>.
    Found 1-bit register for signal <cSpiCommandAck>.
    Found 1-bit register for signal <cSpiDone>.
    Found 1-bit register for signal <cSpiInProgressPrev>.
    Found 1-bit register for signal <cSpiCsDone>.
    Found 1-bit register for signal <cSpiCsInProgressPrev>.
    Found 1-bit register for signal <cFinishCommand>.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <CrioCiSpiEngine> synthesized.

Synthesizing Unit <CcSpiLogic>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/ccspilogic.vhd".
    Found 1-bit register for signal <oSpiClkLast>.
    Found 1-bit register for signal <oCartSelectInt_n>.
    Found 1-bit register for signal <oSpiClkInt>.
    Found 1-bit register for signal <oDataReady>.
    Found 1-bit register for signal <oShiftRisingBeatle>.
    Found 1-bit register for signal <oShiftFallingBeatle>.
    Found 1-bit register for signal <oIgnoreFirstFallingEdge>.
    Found 1-bit register for signal <oIgnoreFallingEdgeStrobeDelayed>.
    Found 1-bit register for signal <oIgnoreFallingEdgeStrobeAfterDelay>.
    Found 1-bit register for signal <oIgnoreFirstFallingEdgeStrobe>.
    Found 1-bit register for signal <oInternalExtraFallingEdgeStrobe>.
    Found 1-bit register for signal <oInternalExtraSourceSynchronousFallingEdgeStrobe>.
    Found 1-bit register for signal <oShiftInProgress>.
    Found 1-bit register for signal <oShiftNext>.
    Found 1-bit register for signal <oContinueSelect>.
    Found 1-bit register for signal <oContinueSelectNext>.
    Found 1-bit register for signal <oMosi>.
    Found 1-bit register for signal <oWaitForCartSelectHigh>.
    Found 1-bit register for signal <oWaitForCartSelectLow>.
    Found 1-bit register for signal <oWaitForSourceSynchToFinish>.
    Found 1-bit register for signal <oCartSelectInProgressInt>.
    Found 8-bit register for signal <oReadRegister>.
    Found 8-bit register for signal <oLoadRegister>.
    Found 8-bit register for signal <oDivideCounter>.
    Found 8-bit register for signal <oSpiRegisterOut>.
    Found 3-bit register for signal <oInputBitCounter>.
    Found 3-bit register for signal <oSpiMuxSelSafe>.
    Found 4-bit register for signal <oOutputBitCounter>.
    Found 7-bit register for signal <oSpiRegisterIn>.
    Found 3-bit adder for signal <oInputBitCounter[2]_GND_4464_o_add_3_OUT> created at line 209.
    Found 4-bit adder for signal <oOutputBitCounter[3]_GND_4464_o_add_63_OUT> created at line 531.
    Found 12-bit adder for signal <n0499> created at line 554.
    Found 12-bit adder for signal <n0447> created at line 1241.
    Found 8-bit subtractor for signal <GND_4464_o_GND_4464_o_sub_53_OUT<7:0>> created at line 1308.
    Found 1-bit 4-to-1 multiplexer for signal <oSpiClkSource[1]_oShiftRisingTrigger_Mux_25_o> created at line 244.
    Found 1-bit 4-to-1 multiplexer for signal <oSpiClkSource[1]_oMisoRisingTrigger_Mux_26_o> created at line 244.
    Found 1-bit 4-to-1 multiplexer for signal <oSpiClkSource[1]_oShiftFallingTrigger_Mux_27_o> created at line 259.
    Found 1-bit 4-to-1 multiplexer for signal <oSpiClkSource[1]_oMisoFallingTrigger_Mux_28_o> created at line 259.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  66 D-type flip-flop(s).
	inferred  94 Multiplexer(s).
Unit <CcSpiLogic> synthesized.

Synthesizing Unit <CcSpiDitherHardcodable>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/ccspiditherhardcodable.vhd".
WARNING:Xst:647 - Input <aSel<2:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <CcSpiDitherHardcodable> synthesized.

Synthesizing Unit <CcSourceSynch>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/ccsourcesynch.vhd".
    Found 1-bit register for signal <oSyncSpiClkDelayed>.
    Found 1-bit register for signal <oMiso_ms>.
    Found 1-bit register for signal <oMiso>.
    Found 1-bit register for signal <oShift>.
    Found 1-bit register for signal <aMisoReg>.
    Summary:
	inferred   5 D-type flip-flop(s).
Unit <CcSourceSynch> synthesized.

Synthesizing Unit <CcSourceSynchFalling>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/ccsourcesynchfalling.vhd".
    Found 1-bit register for signal <aEdgeDetectorOutput>.
    Found 1-bit register for signal <oEdgeDetected_ms>.
    Found 1-bit register for signal <oEdgeDetected>.
    Found 1-bit register for signal <oEdgeDetectedDelayed>.
    Found 1-bit register for signal <oMiso_ms>.
    Found 1-bit register for signal <oMiso>.
    Found 1-bit register for signal <oShift>.
    Found 1-bit register for signal <oEdgeDetectedFE>.
    Found 1-bit register for signal <aMisoReg>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <CcSourceSynchFalling> synthesized.

Synthesizing Unit <CrioCiEeprom>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocieeprom.vhd".
WARNING:Xst:647 - Input <cEepromDataOut<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cEepromModeReleaseRun>.
    Found 1-bit register for signal <cEepromDoneInt>.
    Found 1-bit register for signal <cEepromWriteTimeout>.
    Found 1-bit register for signal <cEepromSpiRunInt>.
    Found 1-bit register for signal <cEepromSpiLastByte>.
    Found 1-bit register for signal <cEepromBusyInt>.
    Found 1-bit register for signal <cWriteRequested>.
    Found 1-bit register for signal <cTimedOut>.
    Found 1-bit register for signal <cEeWriteTimerEnable>.
    Found 1-bit register for signal <cEeWriteTimerDone>.
    Found 1-bit register for signal <cDataValidMask>.
    Found 1-bit register for signal <cEepromModeRequestRun>.
    Found 2-bit register for signal <cDataValidMaskState>.
    Found 2-bit register for signal <cDataValidCount>.
    Found 2-bit register for signal <cEeWriteTimer>.
    Found 5-bit register for signal <cState>.
    Found 8-bit register for signal <cEepromSpiDataOut>.
    Found 8-bit register for signal <cLatchedDataOut>.
    Found 8-bit register for signal <cByteCount>.
    Found 16-bit register for signal <cLatchedAddress>.
    Found finite state machine <FSM_33> for signal <cDataValidMaskState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 13                                             |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforrun                                     |
    | Power Up State     | waitforrun                                     |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_34> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 24                                             |
    | Transitions        | 69                                             |
    | Inputs             | 10                                             |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforrun                                     |
    | Power Up State     | waitforrun                                     |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit adder for signal <cDataValidCount[1]_GND_4471_o_add_3_OUT> created at line 1241.
    Found 2-bit adder for signal <cEeWriteTimer[1]_GND_4471_o_add_68_OUT> created at line 1241.
    Found 8-bit adder for signal <cEepromNumBytes[7]_GND_4471_o_add_73_OUT> created at line 1241.
    Found 8-bit subtractor for signal <GND_4471_o_GND_4471_o_sub_75_OUT<7:0>> created at line 1308.
    WARNING:Xst:2404 -  FFs/Latches <cEepromModeOut<1:1>> (without init value) have a constant value of 0 in block <CrioCiEeprom>.
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred  47 D-type flip-flop(s).
	inferred  51 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <CrioCiEeprom> synthesized.

Synthesizing Unit <CrioCiCartridgeIdentification>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocicartridgeidentification.vhd".
    Found 1-bit register for signal <cCartIdCorrect>.
    Found 1-bit register for signal <cCartIdEepromRun>.
    Found 1-bit register for signal <cCartIdDone>.
    Found 1-bit register for signal <cCartIdCommError>.
    Found 16-bit register for signal <cCartIdEepromAddress>.
    Found 8-bit register for signal <cCartIdEepromNumBytes>.
    Found 4-bit register for signal <cByteCounter>.
    Found 2-bit register for signal <cState>.
    Found finite state machine <FSM_35> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 12                                             |
    | Inputs             | 5                                              |
    | Outputs            | 8                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforrun                                     |
    | Power Up State     | waitforrun                                     |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <cByteCounter[3]_GND_4481_o_add_1_OUT> created at line 197.
    Found 16x8-bit Read Only RAM for signal <cByteCounter[3]_X_447_o_wide_mux_4_OUT>
    Found 4x1-bit Read Only RAM for signal <cByteCounter[2]_PWR_500_o_Mux_10_o>
    Found 8x1-bit Read Only RAM for signal <cByteCounter[3]_X_447_o_Mux_12_o>
    Found 8-bit comparator not equal for signal <n0005> created at line 206
    Summary:
	inferred   3 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred   9 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <CrioCiCartridgeIdentification> synthesized.

Synthesizing Unit <CrioCiInitSequence>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criociinitsequence.vhd".
    Found 1-bit register for signal <cInitDefaultModeIsIdle>.
    Found 1-bit register for signal <cIgnoreRemoval>.
    Found 1-bit register for signal <cCartridgeUnavailable>.
    Found 1-bit register for signal <cInitRun>.
    Found 1-bit register for signal <cCartIdRun>.
    Found 1-bit register for signal <cCommError>.
    Found 4-bit register for signal <cState>.
    Found 3-bit register for signal <cModuleStatus>.
    Found 6-bit register for signal <cTimer>.
    Found finite state machine <FSM_36> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 15                                             |
    | Transitions        | 86                                             |
    | Inputs             | 12                                             |
    | Outputs            | 9                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforpbinit                                  |
    | Power Up State     | waitforpbinit                                  |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit subtractor for signal <GND_4483_o_GND_4483_o_sub_16_OUT<5:0>> created at line 1308.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  15 D-type flip-flop(s).
	inferred  18 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <CrioCiInitSequence> synthesized.

Synthesizing Unit <CrioCiCrcCheck>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocicrccheck.vhd".
    Summary:
	no macro.
Unit <CrioCiCrcCheck> synthesized.

Synthesizing Unit <CrioParallelCrcCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crioparallelcrccore.vhd".
    Found 1-bit register for signal <cRun>.
    Found 8-bit register for signal <cOutputLcl>.
    Found 8-bit register for signal <cInputLcl>.
    Summary:
	inferred  17 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <CrioParallelCrcCore> synthesized.

Synthesizing Unit <CrioCiHsiEngine>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd".
WARNING:Xst:647 - Input <cHsiOutputLength<12:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiOutputData<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiOutputWriteLengthStrobe> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiOutputSendFrameStrobe> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHsiOutputNxReadAck> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cIoDataOut> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cWordsInFrame> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cWriteToMemory> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cWriteToDataMemAssist> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cHsInputDirectAddressedModeEnable> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cInputTransferInProgress> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cInputTransferOverflow> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cInputWordStored> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cInputWordStoreOverflow> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocihsiengine.vhd" line 226: Output port <cStartOfFrameStrobe> of the instance <GenHsiInput.CcHsInputx> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cHsiEnableDone>.
    Found 1-bit register for signal <cRegHsiEnable>.
    Found 1-bit register for signal <cHsiInputTransferCompleteDelayed>.
    Summary:
	inferred   3 D-type flip-flop(s).
Unit <CrioCiHsiEngine> synthesized.

Synthesizing Unit <CcHsInput>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/cchsinput.vhd".
WARNING:Xst:647 - Input <cIoPortIn_Data<31:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cIoPortIn_Data<3:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cPicoBlazePortIn<2:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cIoPortIn_Rd> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cEnableInputInterface>.
    Found 1-bit register for signal <cInputTransferCompleteInt>.
    Found 1-bit register for signal <cInputTransferOverflowInt>.
    Found 1-bit register for signal <cInputWordStoredInt>.
    Found 1-bit register for signal <cInputWordStoreOverflowInt>.
    Found 1-bit register for signal <cPartialWordControl>.
    WARNING:Xst:2404 -  FFs/Latches <cUseBidirPinout<0:0>> (without init value) have a constant value of 0 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cDirectAddressedModeEnable<0:0>> (without init value) have a constant value of 0 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cPartialWordControl<1:1>> (without init value) have a constant value of 0 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cInputEndOfFrameCnt<1:3>> (without init value) have a constant value of 0 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cInputEndOfFrameCnt<4:4>> (without init value) have a constant value of 0 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cSamplingWindowSelect<1:1>> (without init value) have a constant value of 0 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cInputDataFormat<1:1>> (without init value) have a constant value of 0 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cInputWidthMinusOne<1:5>> (without init value) have a constant value of 1 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cWriteToMemoryInt<0:0>> (without init value) have a constant value of 0 in block <CcHsInput>.
    WARNING:Xst:2404 -  FFs/Latches <cWriteToDataMemAssistInt<0:0>> (without init value) have a constant value of 0 in block <CcHsInput>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <CcHsInput> synthesized.

Synthesizing Unit <CcHsInputLogic>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/cchsinputlogic.vhd".
    Found 1-bit register for signal <cDataClkEdgeLater>.
    Found 1-bit register for signal <cDataClkEdgeTwiceLater>.
    Found 1-bit register for signal <cSelectedDataClkEdgeDelayed>.
    Found 1-bit register for signal <cSelectedDataClkEdge>.
    Found 1-bit register for signal <cInFrame>.
    Found 1-bit register for signal <cStartOfFrameStrobe>.
    Found 1-bit register for signal <cEndOfFrame>.
    Found 1-bit register for signal <cWordReceived>.
    Found 1-bit register for signal <cWordReceivedDelayed>.
    Found 1-bit register for signal <cWriteReq>.
    Found 1-bit register for signal <cDataClkLast>.
    Found 7-bit register for signal <cHighCount>.
    Found 7-bit register for signal <cDataShifterLowerBits>.
    Found 32-bit register for signal <cDataShifter>.
    Found 32-bit register for signal <cHsData>.
    Found 3-bit register for signal <cShiftNum<2:0>>.
    Found 5-bit register for signal <cBitCount>.
    Found 8-bit register for signal <cWordCount>.
    Found 8-bit register for signal <cWordsInFrame>.
    Found 7-bit adder for signal <cHighCount[6]_GND_4490_o_add_13_OUT> created at line 1241.
    Found 6-bit adder for signal <n0197> created at line 1241.
    Found 6-bit adder for signal <n0199> created at line 1241.
    Found 6-bit adder for signal <n0201> created at line 1241.
    Found 6-bit adder for signal <n0205> created at line 1241.
    Found 6-bit adder for signal <GND_4490_o_GND_4490_o_add_107_OUT> created at line 1241.
    Found 6-bit adder for signal <GND_4490_o_GND_4490_o_add_109_OUT> created at line 1241.
    Found 6-bit adder for signal <GND_4490_o_GND_4490_o_add_111_OUT> created at line 1241.
    Found 6-bit adder for signal <GND_4490_o_GND_4490_o_add_113_OUT> created at line 1241.
    Found 5-bit adder for signal <cWidthMinusOne[4]_GND_4490_o_add_116_OUT> created at line 1241.
    Found 8-bit adder for signal <cWordCount[7]_GND_4490_o_add_129_OUT> created at line 1241.
    Found 6-bit subtractor for signal <GND_4490_o_GND_4490_o_sub_48_OUT<5:0>> created at line 1308.
    Found 6-bit subtractor for signal <n0277> created at line 0.
    Found 5-bit subtractor for signal <GND_4490_o_GND_4490_o_sub_118_OUT<4:0>> created at line 410.
    Found 1-bit 4-to-1 multiplexer for signal <cDataShifterLowerBits[6]_cData[2]_MUX_9256_o> created at line 296.
    Found 1-bit 4-to-1 multiplexer for signal <cDataShifterLowerBits[6]_cData[1]_MUX_9257_o> created at line 296.
    Found 1-bit 4-to-1 multiplexer for signal <cDataShifterLowerBits[6]_cData[0]_MUX_9258_o> created at line 296.
    Found 1-bit 4-to-1 multiplexer for signal <cDataShifterLowerBits[6]_cData[0]_MUX_9255_o> created at line 293.
    Found 4-bit 4-to-1 multiplexer for signal <GND_4490_o_GND_4490_o_mux_55_OUT> created at line 300.
    Found 3-bit 4-to-1 multiplexer for signal <GND_4490_o_GND_4490_o_mux_91_OUT> created at line 330.
    Found 6-bit 4-to-1 multiplexer for signal <cNextBitCount> created at line 96.
    Found 7-bit comparator equal for signal <cHighCount[6]_cInputEndOfFrameCnt[6]_equal_13_o> created at line 225
    Found 6-bit comparator greater for signal <GND_4490_o_GND_4490_o_LessThan_49_o> created at line 319
    Found 6-bit comparator greater for signal <GND_4490_o_cNextBitCount[5]_LessThan_116_o> created at line 408
    Summary:
	inferred  11 Adder/Subtractor(s).
	inferred 113 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred  49 Multiplexer(s).
Unit <CcHsInputLogic> synthesized.

Synthesizing Unit <CcBarrelShifter>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/ccbarrelshifter.vhd".
    Found 40-bit shifter logical left for signal <oOutput> created at line 43
    Summary:
	inferred   1 Combinational logic shifter(s).
Unit <CcBarrelShifter> synthesized.

Synthesizing Unit <CrioCiInputFlops>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criociinputflops.vhd".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criociinputflops.vhd" line 116: Output port <oInputFallingEdgeSampled> of the instance <SyncDioIn.kcriobustrig.CcInputFlopx> is unconnected or connected to loadless signal.
    Summary:
	no macro.
Unit <CrioCiInputFlops> synthesized.

Synthesizing Unit <CcInputFlop>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/ccinputflop.vhd".
    Found 1-bit register for signal <oInput>.
    Found 1-bit register for signal <oInputFallingEdgeSampled>.
    Found 1-bit register for signal <oInputFallingEdgeSampled_ms>.
    Found 1-bit register for signal <oInput_ms>.
    Summary:
	inferred   4 D-type flip-flop(s).
Unit <CcInputFlop> synthesized.

Synthesizing Unit <Crio9264Resource>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264resource.vhd".
    Summary:
	no macro.
Unit <Crio9264Resource> synthesized.

Synthesizing Unit <Crio9264ResourceCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264resourcecore.vhd".
WARNING:Xst:647 - Input <clkFromResdin<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResIDSelTick<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResClk80Mhz<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResClk80Mhz<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <clkToResdin> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkToResIDSelTick> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkToResClk80Mhz<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <Crio9264ResourceCore> synthesized.

Synthesizing Unit <cRio9264>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264.vhd".
    Set property "IOB = TRUE" for signal <cIdSelOut>.
    Set property "IOB = TRUE" for signal <cSpiFunc>.
    Set property "IOB = TRUE" for signal <cSpiCs_n>.
    Set property "IOB = TRUE" for signal <cSpiClk>.
    Set property "IOB = TRUE" for signal <cSpiMosi>.
    Set property "IOB = TRUE" for signal <cConv_n>.
    Set property "IOB = TRUE" for signal <cEeOutputsEn>.
    Set property "IOB = TRUE" for signal <cIdSelEn>.
    Set property "IOB = TRUE" for signal <cOthersEn>.
WARNING:Xst:647 - Input <cReleaseEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cReleaseEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cAoDataPortEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cAoDataPortEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cAoDataDonePortEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cAoDataDonePortEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cUpdateEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cUpdateEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cUpdateStatusEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cUpdateStatusEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInTrig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInDone_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInConv_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInFunc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInCs_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInMosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInSpiClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264.vhd" line 335: Output port <cStockModPresent> of the instance <cRioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264.vhd" line 335: Output port <cStockDone> of the instance <cRioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264.vhd" line 335: Output port <cStockSpiIdle> of the instance <cRioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264.vhd" line 536: Output port <cCalDebugWarning> of the instance <cRio9264CalData> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <cReleaseEnableOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <cAoDataPortEnableOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <cUpdateEnableOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <cUpdateStatusEnableOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	inferred  10 Multiplexer(s).
Unit <cRio9264> synthesized.

Synthesizing Unit <cRioStock_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostock.vhd".
    Summary:
	inferred   7 Multiplexer(s).
Unit <cRioStock_1> synthesized.

Synthesizing Unit <cRioStockModuleId_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockmoduleid.vhd".
    Found 1-bit register for signal <cStockEeRunMI>.
    Found 1-bit register for signal <cStockDoneMI>.
    Found 2-bit register for signal <cStockModStatusMI>.
    Found 2-bit register for signal <cStockInternalModIdStatus>.
    Found 16-bit register for signal <cStockEeAddrMI>.
    Found 33-bit register for signal <cStockErrorMI>.
    Found 3-bit register for signal <cCount>.
    Found 4-bit register for signal <cState>.
    Found 2-bit register for signal <cStockReqModeMI>.
    Found finite state machine <FSM_37> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 23                                             |
    | Inputs             | 7                                              |
    | Outputs            | 7                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | nomodulepresent                                |
    | Power Up State     | nomodulepresent                                |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit subtractor for signal <GND_4694_o_GND_4694_o_sub_19_OUT<2:0>> created at line 163.
    Found 8x57-bit Read Only RAM for signal <_n0418>
    Found 8-bit comparator equal for signal <GND_4694_o_cStockDataEE[7]_equal_23_o> created at line 162
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  60 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  10 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockModuleId_1> synthesized.

Synthesizing Unit <cRioStockModeSelector>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockmodeselector.vhd".
    Found 1-bit register for signal <cFuncOut>.
    Found 1-bit register for signal <cStockSelDoneMS>.
    Found 1-bit register for signal <cIdSelOut>.
    Found 1-bit register for signal <cEeOutputsEn>.
    Found 1-bit register for signal <cOthersEn>.
    Found 1-bit register for signal <cIdSelEn>.
    Found 1-bit register for signal <cTristateDelay>.
    Found 1-bit register for signal <cOneTick>.
    Found 1-bit register for signal <cGo_ms>.
    Found 1-bit register for signal <cGo>.
    Found 1-bit register for signal <cModeOneDelayComplete>.
    Found 1-bit register for signal <cModeTwoDelayComplete>.
    Found 1-bit register for signal <cModeThreeDelayComplete>.
    Found 1-bit register for signal <cModeFourDelayComplete>.
    Found 1-bit register for signal <cWaitForNoModuleDetection>.
    Found 1-bit register for signal <cIgnoreTimer2>.
    Found 1-bit register for signal <cIdSelIn_ms>.
    Found 1-bit register for signal <cIdSelInPreFilter>.
    Found 1-bit register for signal <cIdSelIn>.
    Found 2-bit register for signal <cStockModPresentMS>.
    Found 4-bit register for signal <cState>.
    Found 5-bit register for signal <cTimer>.
    Found 6-bit register for signal <cPowerUpTimer>.
    Found 7-bit register for signal <cTimer2>.
    Found 2-bit register for signal <cIdSelFilterCount>.
    Found finite state machine <FSM_38> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 15                                             |
    | Transitions        | 52                                             |
    | Inputs             | 23                                             |
    | Outputs            | 19                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | reset                                          |
    | Power Up State     | reset                                          |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit adder for signal <cTimer[4]_GND_4696_o_add_0_OUT> created at line 1241.
    Found 7-bit adder for signal <cTimer2[6]_GND_4696_o_add_1_OUT> created at line 1241.
    Found 6-bit adder for signal <cPowerUpTimer[5]_GND_4696_o_add_6_OUT> created at line 1241.
    Found 2-bit adder for signal <cIdSelFilterCount[1]_GND_4696_o_add_146_OUT> created at line 507.
    Found 1-bit 4-to-1 multiplexer for signal <cStockReqModeMS[1]_PWR_517_o_Mux_144_o> created at line 441.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  41 D-type flip-flop(s).
	inferred  76 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockModeSelector> synthesized.

Synthesizing Unit <cRioStockSpiEngine_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockspiengine.vhd".
    Set property "IOB = TRUE" for signal <cMiso>.
    Found 1-bit register for signal <cCs_n>.
    Found 1-bit register for signal <cSpiClk>.
    Found 1-bit register for signal <cStockIdleSPI>.
    Found 1-bit register for signal <cHoldCs>.
    Found 1-bit register for signal <cSpiDone>.
    Found 1-bit register for signal <cSpiDoneDly>.
    Found 1-bit register for signal <cLdDataInDly>.
    Found 8-bit register for signal <cTimer>.
    Found 8-bit register for signal <cOutShiftReg>.
    Found 8-bit register for signal <cInReg>.
    Found 4-bit register for signal <cNumBits>.
    Found 4-bit register for signal <cState>.
    Found finite state machine <FSM_39> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 25                                             |
    | Inputs             | 5                                              |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit adder for signal <cTimer[7]_GND_4698_o_add_0_OUT> created at line 1241.
    Found 8-bit subtractor for signal <GND_4698_o_GND_4698_o_sub_4_OUT<7:0>> created at line 1308.
    Found 8-bit subtractor for signal <GND_4698_o_GND_4698_o_sub_10_OUT<7:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_4698_o_GND_4698_o_sub_20_OUT<3:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_4698_o_GND_4698_o_sub_26_OUT<3:0>> created at line 1308.
    Found 8-bit comparator equal for signal <cTimer[7]_GND_4698_o_equal_5_o> created at line 150
    Found 8-bit comparator equal for signal <cTimer[7]_GND_4698_o_equal_11_o> created at line 160
INFO:Xst:2774 - HDL ADVISOR - IOB property attached to signal cMiso may hinder XST clustering optimizations.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  35 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  30 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockSpiEngine_1> synthesized.

Synthesizing Unit <cRioStockEePromRead>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockeepromread.vhd".
    Found 1-bit register for signal <cStockSpiRunEE>.
    Found 1-bit register for signal <cStockDoneEE>.
    Found 1-bit register for signal <cStockSpiCommandEE_HoldCs>.
    Found 8-bit register for signal <cStockDataEE>.
    Found 8-bit register for signal <cStockSpiDataOutEE>.
    Found 3-bit register for signal <cState>.
    Found 4-bit register for signal <cStockSpiCommandEE_NumBits>.
    Found finite state machine <FSM_40> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 12                                             |
    | Inputs             | 3                                              |
    | Outputs            | 6                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  23 D-type flip-flop(s).
	inferred   3 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockEePromRead> synthesized.

Synthesizing Unit <cRio9264EnableChainHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264enablechainhandler.vhd".
    Found 1-bit register for signal <cEepromRun>.
    Found 1-bit register for signal <cOkToUpdate>.
    Found 1-bit register for signal <cBufferWritten>.
    Found 1-bit register for signal <cModuleReId>.
    Found 1-bit register for signal <cRequestDone>.
    Found 1-bit register for signal <cEcEePromDone>.
    Found 4-bit register for signal <cState>.
    Found finite state machine <FSM_41> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 25                                             |
    | Inputs             | 10                                             |
    | Outputs            | 5                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforid                                      |
    | Power Up State     | waitforid                                      |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9264EnableChainHandler> synthesized.

Synthesizing Unit <CrioEepromRead_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crioeepromread.vhd".
    Found 1-bit register for signal <cModuleEeRun>.
    Found 1-bit register for signal <cEepromDone>.
    Found 8-bit register for signal <cEepromData>.
    Found 3-bit register for signal <cState>.
    Found 2-bit register for signal <cModuleReqMode>.
    Found finite state machine <FSM_42> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <CrioEepromRead_1> synthesized.

Synthesizing Unit <cRio9264IoHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264iohandler.vhd".
    Set property "syn_keep = true" for signal <ssMisoShiftReg>.
WARNING:Xst:647 - Input <cStockSpiDataIn<7:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cClearStatusCached> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <SsClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aSpiMiso> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cModuleReadyInt>.
    Found 1-bit register for signal <cUpdateStrobe>.
    Found 1-bit register for signal <cWriteDone>.
    Found 1-bit register for signal <cModuleSpiRun>.
    Found 1-bit register for signal <cModuleSpiCommand_HoldCs>.
    Found 1-bit register for signal <cWriteStrobeOut>.
    Found 1-bit register for signal <cLatchedStrobe>.
    Found 1-bit register for signal <cPowerupTimer>.
    Found 1-bit register for signal <cIsLastChannelLatched>.
    Found 5-bit register for signal <cInitChannel>.
    Found 8-bit register for signal <cModuleSpiDataOut>.
    Found 4-bit register for signal <cState>.
    Found 4-bit register for signal <cModuleSpiCommand_NumBits>.
    Found 3-bit register for signal <cTimer>.
    Found finite state machine <FSM_43> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 26                                             |
    | Inputs             | 12                                             |
    | Outputs            | 8                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idlenotready                                   |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <cTimer[2]_GND_4705_o_add_0_OUT> created at line 1241.
    Found 5-bit adder for signal <cInitChannel[4]_GND_4705_o_add_33_OUT> created at line 1241.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  29 D-type flip-flop(s).
	inferred  31 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9264IoHandler> synthesized.

Synthesizing Unit <cRio9264UpdateHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264updatehandler.vhd".
    Found 1-bit register for signal <cConv_n_out>.
    Found 1-bit register for signal <cConvertDone>.
    Found 1-bit register for signal <cUpdateStrobed>.
    Found 6-bit register for signal <cCurTimeCount>.
    Found 2-bit register for signal <cState>.
    Found finite state machine <FSM_44> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit adder for signal <cCurTimeCount[5]_GND_4707_o_add_0_OUT> created at line 1241.
    Found 6-bit 3-to-1 multiplexer for signal <cState[1]_X_469_o_wide_mux_11_OUT> created at line 81.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9264UpdateHandler> synthesized.

Synthesizing Unit <cRio9264GetCalConst>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264getcalconst.vhd".
    Found 1-bit register for signal <cGetCalConstIdle>.
    Found 1-bit register for signal <cEePropRun>.
    Found 1-bit register for signal <cCalMemWrEn>.
    Found 1-bit register for signal <cClearCrc>.
    Found 1-bit register for signal <cUpdateCrc>.
    Found 1-bit register for signal <cCrcErrorBuf>.
    Found 1-bit register for signal <cRecipRun>.
    Found 2-bit register for signal <cModStatusOut>.
    Found 2-bit register for signal <cMultInSel>.
    Found 3-bit register for signal <cCountCalBytes>.
    Found 6-bit register for signal <cCountCalWords>.
    Found 9-bit register for signal <cCalEePropAddrBuf>.
    Found 32-bit register for signal <cCalDataRaw>.
    Found 36-bit register for signal <cMultBuf>.
    Found 14-bit register for signal <cCalMemOffsetData>.
    Found 45-bit register for signal <cAccum>.
    Found 4-bit register for signal <cCalMemWrAddr>.
    Found 4-bit register for signal <cState>.
    Found finite state machine <FSM_45> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 23                                             |
    | Inputs             | 9                                              |
    | Outputs            | 8                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waittorungetcalconst                           |
    | Power Up State     | waittorungetcalconst                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit adder for signal <cCalEePropAddrBuf[8]_GND_4709_o_add_18_OUT> created at line 1241.
    Found 45-bit adder for signal <cMultBuf[26]_cAccum[43]_add_63_OUT> created at line 1548.
    Found 6-bit adder for signal <cCountCalWords[5]_GND_4709_o_add_68_OUT> created at line 1241.
    Found 45-bit adder for signal <cMultBuf[9]_cAccum[43]_add_74_OUT> created at line 1548.
    Found 3-bit adder for signal <cCountCalBytes[2]_GND_4709_o_add_83_OUT> created at line 1241.
    Found 4-bit subtractor for signal <GND_4709_o_GND_4709_o_sub_81_OUT<3:0>> created at line 1308.
    Found 3-bit comparator greater for signal <cCountCalBytes[2]_GND_4709_o_LessThan_20_o> created at line 248
    Summary:
	inferred   6 Adder/Subtractor(s).
	inferred 160 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  45 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9264GetCalConst> synthesized.

Synthesizing Unit <cRio9264CalReciprocal>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264calreciprocal.vhd".
    Found 1-bit register for signal <cRecipDone>.
    Found 1-bit register for signal <cRecipRunning>.
    Found 18-bit register for signal <cCurVal>.
    Found 54-bit register for signal <cAccum>.
    Found 36-bit register for signal <cMultBuf>.
    Found 2-bit register for signal <cMultInSel>.
    Found 5-bit register for signal <cIterCount>.
    Found 34-bit register for signal <cFirstResult>.
    Found 3-bit register for signal <cState>.
    Found 2-bit register for signal <cCalcStage>.
    Found finite state machine <FSM_46> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 11                                             |
    | Inputs             | 3                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_47> for signal <cCalcStage>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 12                                             |
    | Inputs             | 3                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | first                                          |
    | Power Up State     | notstarted                                     |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 54-bit adder for signal <GND_4710_o_cAccum[53]_add_3_OUT> created at line 131.
    Found 54-bit adder for signal <cMultBuf[19]_cAccum[53]_add_4_OUT> created at line 131.
    Found 5-bit adder for signal <cIterCount[4]_GND_4710_o_add_6_OUT> created at line 1241.
    Found 38-bit subtractor for signal <GND_4710_o_GND_4710_o_sub_10_OUT<37:0>> created at line 2010.
    Found 5-bit comparator greater for signal <cIterCount[4]_GND_4710_o_LessThan_14_o> created at line 282
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 151 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  17 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <cRio9264CalReciprocal> synthesized.

Synthesizing Unit <cRio9264CalData>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9264caldata.vhd".
    Set property "ram_style = distributed" for signal <cList>.
WARNING:Xst:647 - Input <cMultOut<35:34>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 16x20-bit single-port RAM <Mram_cList> for signal <cList>.
    Found 1-bit register for signal <cWriteStrobeOutBuf>.
    Found 37-bit register for signal <cCalDataTemp>.
    Found 3-bit register for signal <cState>.
    Found 36-bit register for signal <cMultBuf>.
    Found 18-bit register for signal <cAoDataInOffsetFxp>.
    Found 2-bit register for signal <cMultInSel>.
    Found finite state machine <FSM_48> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 8                                              |
    | Transitions        | 10                                             |
    | Inputs             | 2                                              |
    | Outputs            | 6                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 37-bit adder for signal <cCalDataTemp[16]_cMultBuf[16]_add_27_OUT> created at line 1548.
    Found 20-bit adder for signal <n0119> created at line 1548.
    Found 21-bit subtractor for signal <GND_4713_o_GND_4713_o_sub_4_OUT<20:0>> created at line 2010.
    Summary:
	inferred   1 RAM(s).
	inferred   3 Adder/Subtractor(s).
	inferred  94 D-type flip-flop(s).
	inferred  18 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9264CalData> synthesized.

Synthesizing Unit <cRioCalParallelCrc>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocalparallelcrc.vhd".
    Summary:
	no macro.
Unit <cRioCalParallelCrc> synthesized.

Synthesizing Unit <cRioCalMemory_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocalmemory.vhd".
    Set property "ram_style = distributed" for signal <cCalMemData>.
    Found 16x32-bit single-port RAM <Mram_cCalMemData> for signal <cCalMemData>.
    Summary:
	inferred   1 RAM(s).
Unit <cRioCalMemory_2> synthesized.

Synthesizing Unit <ViControl>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/vicontrol.vhd".
    Set property "equivalent_register_removal = no".
    Set property "syn_keep = true" for signal <rDiagramResetAssertionErr>.
    Set property "syn_keep = true" for signal <rEnableIn>.
    Set property "syn_keep = true" for signal <rEnableClear>.
    Set property "syn_keep = true" for signal <EnableInBlk.tEnableIn_ms>.
    Set property "syn_keep = true" for signal <EnableInBlk.bEnableIn_ms>.
    Set property "syn_keep = true" for signal <EnableClearBlk.bEnableClear_ms>.
    Set property "syn_keep = true" for signal <EnableClearBlk.tEnableClear_ms>.
    Set property "syn_keep = true" for signal <DerivedClkLockBlk.bDerivedClkLostLock_ms>.
    Set property "syn_keep = true" for signal <GatedClkStartupErrBlk.bGatedClkStartupErr_ms>.
    Set property "syn_keep = true" for signal <EnableDeassertionErrBlk.bEnableDeassertionErr_ms>.
    Set property "syn_keep = true" for signal <DiagramResetAssertionErrBlk.bDiagramResetAssertionErr_ms>.
WARNING:Xst:647 - Input <bHostReadIn<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bHostWriteIn<33:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bHostWriteIn<2:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <bTimeout>.
    Found 1-bit register for signal <EnableInBlk.tEnableIn_ms>.
    Found 1-bit register for signal <EnableInBlk.tEnableInLoc>.
    Found 1-bit register for signal <rEnableClear>.
    Found 1-bit register for signal <EnableClearBlk.tEnableClear_ms>.
    Found 1-bit register for signal <EnableClearBlk.tEnableClearLoc>.
    Found 1-bit register for signal <EnableOutBlk.tDiagramEnableOutReg>.
    Found 1-bit register for signal <EnableOutBlk.bEnableOut_ms>.
    Found 1-bit register for signal <bEnableOut>.
    Found 3-bit register for signal <EnableInBlk.rEnableInState>.
    Found 4-bit register for signal <EnableInBlk.rTimerCount>.
    Found 1-bit register for signal <rEnableIn>.
    Found 1-bit register for signal <EnableInBlk.rEnableClksForViRunLoc>.
    Found 1-bit register for signal <EnableInBlk.bEnableIn_ms>.
    Found 1-bit register for signal <bEnableIn>.
    Found 1-bit register for signal <EnableClearBlk.bEnableClear_ms>.
    Found 1-bit register for signal <bEnableClear>.
    Found 1-bit register for signal <DerivedClkLockBlk.rDerivedClkLostLock>.
    Found 1-bit register for signal <DerivedClkLockBlk.bDerivedClkLostLock_ms>.
    Found 1-bit register for signal <bDerivedClkLostLock>.
    Found 1-bit register for signal <GatedClkStartupErrBlk.rGatedClkStartupErr>.
    Found 1-bit register for signal <GatedClkStartupErrBlk.bGatedClkStartupErr_ms>.
    Found 1-bit register for signal <bGatedClkStartupErr>.
    Found 1-bit register for signal <EnableDeassertionErrBlk.rEnableDeassertionErr>.
    Found 1-bit register for signal <EnableDeassertionErrBlk.bEnableDeassertionErr_ms>.
    Found 1-bit register for signal <bEnableDeassertionErr>.
    Found 1-bit register for signal <DiagramResetAssertionErrBlk.bDiagramResetAssertionErr_ms>.
    Found 1-bit register for signal <bDiagramResetAssertionErr>.
INFO:Xst:1799 - State waituntilinternalclocksbecomevalid is never reached in FSM <EnableInBlk.rEnableInState>.
INFO:Xst:1799 - State enableindeassertionnotsupportederr is never reached in FSM <EnableInBlk.rEnableInState>.
    Found finite state machine <FSM_49> for signal <EnableInBlk.rEnableInState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 9                                              |
    | Inputs             | 4                                              |
    | Outputs            | 5                                              |
    | Clock              | ReliableClk (rising_edge)                      |
    | Reset              | rDiagramResetStatus (positive)                 |
    | Reset type         | synchronous                                    |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit subtractor for signal <GND_4729_o_GND_4729_o_sub_14_OUT<3:0>> created at line 582.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  29 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <ViControl> synthesized.

Synthesizing Unit <SafeBusCrossing_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/safebuscrossing.vhd".
    Set property "equivalent_register_removal = no".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/safebuscrossing.vhd" line 280: Output port <iStoredData> of the instance <ClockDomainCrossing.BusClkToReliableClkHS> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/safebuscrossing.vhd" line 280: Output port <iOResetStatus> of the instance <ClockDomainCrossing.BusClkToReliableClkHS> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <bPushEnDly>.
    Found 1-bit register for signal <bPushDly>.
    Found 1-bit register for signal <bReadyLoc>.
    Found 2-bit register for signal <ClockDomainCrossing.bDataDly>.
    Found 2-bit register for signal <ClockDomainCrossing.bPushEnState>.
    Found finite state machine <FSM_50> for signal <ClockDomainCrossing.bPushEnState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Clock              | BusClk (rising_edge)                           |
    | Reset              | aBusReset (positive)                           |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <SafeBusCrossing_1> synthesized.

Synthesizing Unit <HandshakeBaseResetCross_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd".
    Set property "syn_keep = true" for signal <iPush>.
    Set property "syn_keep = true" for signal <iDlyPush>.
    Set property "syn_keep = true" for signal <iLclReady>.
    Set property "use_clock_enable = yes" for signal <oPushToggleToReady>.
    Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>.
    Set property "syn_keep = true" for signal <BlkOut.oDataAckClkEnable>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_direct_enable". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.
WARNING:Xst:647 - Input <aResetToDlyPush<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResetToIResetFast<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aPushToggleDly<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd" line 382: Output port <c1ResetFast> of the instance <BlkOut.SyncOReset> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <BlkRdy.iRdyPushToggle>.
    Found 1-bit register for signal <iLclReady>.
    Found 1-bit register for signal <iDlyPush>.
    Found 1-bit register for signal <BlkOut.oPushToggle1>.
    Found 1-bit register for signal <BlkOut.oPushToggle2>.
    Found 1-bit register for signal <oDataValid>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <HandshakeBaseResetCross_4> synthesized.

Synthesizing Unit <DiagramReset>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/diagramreset.vhd".
    Set property "equivalent_register_removal = no".
    Set property "syn_maxfan = 1000000" for signal <rDiagramReset>.
    Set property "syn_maxfan = 1000000" for signal <aDiagramReset>.
    Set property "syn_keep = true" for signal <bDiagramResetForHost_ms>.
    Set property "syn_keep = true" for signal <rDiagramResetForHost>.
    Set property "KEEP = TRUE" for signal <DiagramResetFSM.rStartFsmOnDld>.
    Set property "KEEP = TRUE" for signal <DiagramResetFSM.rStartFsmOnDldDly>.
    Set property "KEEP = TRUE" for signal <DiagramResetFSM.rStartFsmOnDld_ms>.
    Set property "syn_keep = true" for signal <DiagramResetRegisterBlk.rDiagramResetLoc>.
    Set property "syn_keep = true" for signal <DiagramResetRegisterBlk.aDiagramResetLoc>.
WARNING:Xst:647 - Input <bHostReadIn<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bHostWriteIn<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <bHostWriteIn<3:33>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/diagramreset.vhd" line 355: Output port <rData> of the instance <HostWtAccessBlk.BusClkToReliableClkHS> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <DiagramResetFSM.rStartFsmOnDld>.
    Found 1-bit register for signal <DiagramResetFSM.rStartFsmOnDldDly>.
    Found 4-bit register for signal <DiagramResetFSM.rDiagramResetState>.
    Found 6-bit register for signal <DiagramResetFSM.rTimerCount>.
    Found 1-bit register for signal <DiagramResetFSM.rDcmPllSourceClksValidLoc>.
    Found 1-bit register for signal <DiagramResetFSM.rInternalClksValidLoc>.
    Found 1-bit register for signal <DiagramResetFSM.rDiagramResetAssertionErrLoc>.
    Found 1-bit register for signal <rDiagramResetForHost>.
    Found 1-bit register for signal <bDiagramResetForHost_ms>.
    Found 1-bit register for signal <bDiagramResetForHost>.
    Found 1-bit register for signal <DiagramResetFSM.rStartFsmOnDld_ms>.
INFO:Xst:1799 - State waitforclkenablerequest is never reached in FSM <DiagramResetFSM.rDiagramResetState>.
INFO:Xst:1799 - State diagrstassertionnotsupportederr is never reached in FSM <DiagramResetFSM.rDiagramResetState>.
    Found finite state machine <FSM_51> for signal <DiagramResetFSM.rDiagramResetState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 15                                             |
    | Inputs             | 7                                              |
    | Outputs            | 5                                              |
    | Clock              | ReliableClk (rising_edge)                      |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit subtractor for signal <GND_4830_o_GND_4830_o_sub_22_OUT<5:0>> created at line 688.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  14 D-type flip-flop(s).
	inferred  23 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <DiagramReset> synthesized.

Synthesizing Unit <SafeBusCrossing_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/safebuscrossing.vhd".
    Set property "equivalent_register_removal = no".
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/safebuscrossing.vhd" line 280: Output port <iStoredData> of the instance <ClockDomainCrossing.BusClkToReliableClkHS> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/safebuscrossing.vhd" line 280: Output port <iOResetStatus> of the instance <ClockDomainCrossing.BusClkToReliableClkHS> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <bPushEnDly>.
    Found 1-bit register for signal <bPushDly>.
    Found 1-bit register for signal <bReadyLoc>.
    Found 2-bit register for signal <ClockDomainCrossing.bPushEnState>.
    Found finite state machine <FSM_52> for signal <ClockDomainCrossing.bPushEnState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 2                                              |
    | Clock              | BusClk (rising_edge)                           |
    | Reset              | aBusReset (positive)                           |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    WARNING:Xst:2404 -  FFs/Latches <ClockDomainCrossing.bDataDly<0><0:0>> (without init value) have a constant value of 0 in block <SafeBusCrossing_2>.
    Summary:
	inferred   3 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <SafeBusCrossing_2> synthesized.

Synthesizing Unit <HandshakeBaseResetCross_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd".
    Set property "syn_keep = true" for signal <iPush>.
    Set property "syn_keep = true" for signal <iDlyPush>.
    Set property "syn_keep = true" for signal <iLclReady>.
    Set property "use_clock_enable = yes" for signal <oPushToggleToReady>.
    Set property "syn_maxfan = 1000000" for signal <BlkOut.oPushToggle0_ms>.
    Set property "syn_keep = true" for signal <BlkOut.oDataAckClkEnable>.
WARNING:Xst:37 - Detected unknown constraint/property "syn_direct_enable". This constraint/property is not supported by the current software release and will be ignored.
    Set property "syn_maxfan = 1000000" for signal <BlkRdy.iRdyPushToggle_ms>.
WARNING:Xst:647 - Input <aResetToDlyPush<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aResetToIResetFast<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aPushToggleDly<31:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/handshakebaseresetcross.vhd" line 382: Output port <c1ResetFast> of the instance <BlkOut.SyncOReset> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <BlkRdy.iRdyPushToggle>.
    Found 1-bit register for signal <iLclReady>.
    Found 1-bit register for signal <iDlyPush>.
    Found 1-bit register for signal <BlkOut.oPushToggle1>.
    Found 1-bit register for signal <BlkOut.oPushToggle2>.
    Found 1-bit register for signal <oDataValid>.
    Summary:
	inferred   6 D-type flip-flop(s).
Unit <HandshakeBaseResetCross_5> synthesized.

Synthesizing Unit <DFlopSlvResetVal_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/dflopslvresetval.vhd".
    Summary:
	no macro.
Unit <DFlopSlvResetVal_5> synthesized.

Synthesizing Unit <ViSignature>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/visignature.vhd".
WARNING:Xst:647 - Input <clkHostReadFromReshold<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <ViSignature> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cFpgaReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn>.
    Found 1-bit register for signal <cFpgaWriteToRes>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <NiFpgaCtrlIndRegister_1> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgahostaccessibleregister.vhd".
    Found 1-bit register for signal <cQ>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <NiFpgaHostAccessibleRegister_1> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd" line 331: Output port <cFpgaDataEnable> of the instance <PlainIndicator.PlainIndicator> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cFpgaWriteToRes>.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <NiFpgaCtrlIndRegister_2> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgahostaccessibleregister.vhd".
    Found 2-bit register for signal <cQ>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <NiFpgaHostAccessibleRegister_2> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd" line 331: Output port <cFpgaDataEnable> of the instance <PlainIndicator.PlainIndicator> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cFpgaWriteToRes>.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <NiFpgaCtrlIndRegister_3> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgahostaccessibleregister.vhd".
    Found 33-bit register for signal <cQ>.
    Summary:
	inferred  33 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <NiFpgaHostAccessibleRegister_3> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd" line 331: Output port <cFpgaDataEnable> of the instance <PlainIndicator.PlainIndicator> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cFpgaWriteToRes>.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <NiFpgaCtrlIndRegister_4> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd" line 331: Output port <cFpgaDataEnable> of the instance <PlainIndicator.PlainIndicator> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cFpgaWriteToRes>.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <NiFpgaCtrlIndRegister_5> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgahostaccessibleregister.vhd".
    Found 1-bit register for signal <cQ>.
    Summary:
	inferred   1 D-type flip-flop(s).
	inferred   2 Multiplexer(s).
Unit <NiFpgaHostAccessibleRegister_4> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_6>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd" line 331: Output port <cFpgaDataEnable> of the instance <PlainIndicator.PlainIndicator> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cFpgaWriteToRes>.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <NiFpgaCtrlIndRegister_6> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgahostaccessibleregister.vhd".
    Found 816-bit register for signal <cQ>.
    Summary:
	inferred 816 D-type flip-flop(s).
Unit <NiFpgaHostAccessibleRegister_5> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_7>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd" line 331: Output port <cFpgaDataEnable> of the instance <PlainIndicator.PlainIndicator> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cFpgaWriteToRes>.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <NiFpgaCtrlIndRegister_7> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_6>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgahostaccessibleregister.vhd".
    Found 336-bit register for signal <cQ>.
    Summary:
	inferred 336 D-type flip-flop(s).
Unit <NiFpgaHostAccessibleRegister_6> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_8>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd" line 331: Output port <cFpgaDataEnable> of the instance <PlainIndicator.PlainIndicator> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cFpgaWriteToRes>.
    Found 1-bit register for signal <rFpgaDelayedWriteEnableIn>.
    Summary:
	inferred   2 D-type flip-flop(s).
Unit <NiFpgaCtrlIndRegister_8> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_7>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgahostaccessibleregister.vhd".
    Found 736-bit register for signal <cQ>.
    Summary:
	inferred 736 D-type flip-flop(s).
Unit <NiFpgaHostAccessibleRegister_7> synthesized.

Synthesizing Unit <NiFpgaCtrlIndRegister_9>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgactrlindregister.vhd".
WARNING:Xst:647 - Input <cFpgaReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostReadFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cHostWriteFromRes<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaCtrlIndRegister_9> synthesized.

Synthesizing Unit <NiFpgaHostAccessibleRegister_8>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgahostaccessibleregister.vhd".
    Found 8-bit register for signal <cQ>.
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaHostAccessibleRegister_8> synthesized.

Synthesizing Unit <Crio9403Resource>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403resource.vhd".
    Summary:
	no macro.
Unit <Crio9403Resource> synthesized.

Synthesizing Unit <Crio9403ResourceCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403resourcecore.vhd".
WARNING:Xst:647 - Input <clkFromResdin<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResIDSelTick<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkEepromFromReshold<3:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkDiPortFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <clkErrorToReshold<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkDiPortToReshold<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <Crio9403ResourceCore> synthesized.

Synthesizing Unit <cRio9403>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403.vhd".
    Set property "IOB = TRUE" for signal <cConv_n>.
    Set property "IOB = TRUE" for signal <cEeOutputsEn>.
    Set property "IOB = TRUE" for signal <cIdSelEn>.
    Set property "IOB = TRUE" for signal <cIdSelOut>.
    Set property "IOB = TRUE" for signal <cOthersEn>.
    Set property "IOB = TRUE" for signal <cSpiClk>.
    Set property "IOB = TRUE" for signal <cSpiCs_n>.
    Set property "IOB = TRUE" for signal <cSpiFunc>.
    Set property "IOB = TRUE" for signal <cSpiMosi>.
WARNING:Xst:647 - Input <aCrioBusInOClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInTrig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInDone_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInConv_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInFunc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInCs_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInMosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInSpiClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403.vhd" line 295: Output port <cStockModPresent> of the instance <cRioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403.vhd" line 295: Output port <cStockDone> of the instance <cRioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403.vhd" line 295: Output port <cStockSpiIdle> of the instance <cRioStock> is unconnected or connected to loadless signal.
    Summary:
	inferred   1 Multiplexer(s).
Unit <cRio9403> synthesized.

Synthesizing Unit <cRio9403EnableChainHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403enablechainhandler.vhd".
    Found 1-bit register for signal <cEePropRun>.
    Found 1-bit register for signal <cSetOutputDataRun>.
    Found 1-bit register for signal <cLineDirectionRun>.
    Found 1-bit register for signal <cDioRun>.
    Found 1-bit register for signal <cModuleReId>.
    Found 1-bit register for signal <cReWriteConfig>.
    Found 1-bit register for signal <cReWriteDone>.
    Found 1-bit register for signal <cReWriteReq>.
    Found 4-bit register for signal <cState>.
    Found 4-bit register for signal <cNextState>.
    Found 4-bit 11-to-1 multiplexer for signal <cState[3]_X_505_o_wide_mux_23_OUT> created at line 102.
    Found 4-bit 3-to-1 multiplexer for signal <cState[3]_GND_4974_o_mux_4_OUT> created at line 109.
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred  41 Multiplexer(s).
Unit <cRio9403EnableChainHandler> synthesized.

Synthesizing Unit <cRioStock_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostock.vhd".
WARNING:Xst:647 - Input <FClk80> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred   7 Multiplexer(s).
Unit <cRioStock_2> synthesized.

Synthesizing Unit <cRioStockModuleId_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockmoduleid.vhd".
    Found 1-bit register for signal <cStockEeRunMI>.
    Found 1-bit register for signal <cStockDoneMI>.
    Found 2-bit register for signal <cStockModStatusMI>.
    Found 2-bit register for signal <cStockInternalModIdStatus>.
    Found 16-bit register for signal <cStockEeAddrMI>.
    Found 33-bit register for signal <cStockErrorMI>.
    Found 3-bit register for signal <cCount>.
    Found 4-bit register for signal <cState>.
    Found 2-bit register for signal <cStockReqModeMI>.
    Found finite state machine <FSM_53> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 23                                             |
    | Inputs             | 7                                              |
    | Outputs            | 7                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | nomodulepresent                                |
    | Power Up State     | nomodulepresent                                |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit subtractor for signal <GND_4977_o_GND_4977_o_sub_19_OUT<2:0>> created at line 163.
    Found 8x57-bit Read Only RAM for signal <_n0418>
    Found 8-bit comparator equal for signal <GND_4977_o_cStockDataEE[7]_equal_23_o> created at line 162
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  60 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  10 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockModuleId_2> synthesized.

Synthesizing Unit <cRioStockSpiEngine_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockspiengine.vhd".
    Set property "IOB = TRUE" for signal <cMiso>.
    Found 1-bit register for signal <cCs_n>.
    Found 1-bit register for signal <cSpiClk>.
    Found 1-bit register for signal <cStockIdleSPI>.
    Found 1-bit register for signal <cHoldCs>.
    Found 1-bit register for signal <cSpiDone>.
    Found 1-bit register for signal <cLdDataInDly>.
    Found 8-bit register for signal <cTimer>.
    Found 8-bit register for signal <cOutShiftReg>.
    Found 8-bit register for signal <cInReg>.
    Found 4-bit register for signal <cNumBits>.
    Found 4-bit register for signal <cState>.
    Found finite state machine <FSM_54> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 25                                             |
    | Inputs             | 5                                              |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit adder for signal <cTimer[7]_GND_4979_o_add_0_OUT> created at line 1241.
    Found 8-bit subtractor for signal <GND_4979_o_GND_4979_o_sub_4_OUT<7:0>> created at line 1308.
    Found 8-bit subtractor for signal <GND_4979_o_GND_4979_o_sub_10_OUT<7:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_4979_o_GND_4979_o_sub_20_OUT<3:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_4979_o_GND_4979_o_sub_26_OUT<3:0>> created at line 1308.
    Found 8-bit comparator equal for signal <cTimer[7]_GND_4979_o_equal_5_o> created at line 150
    Found 8-bit comparator equal for signal <cTimer[7]_GND_4979_o_equal_11_o> created at line 160
INFO:Xst:2774 - HDL ADVISOR - IOB property attached to signal cMiso may hinder XST clustering optimizations.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  34 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  28 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockSpiEngine_2> synthesized.

Synthesizing Unit <cRio9403CommHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403commhandler.vhd".
    Summary:
	inferred   2 Multiplexer(s).
Unit <cRio9403CommHandler> synthesized.

Synthesizing Unit <cRio9403DioHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403diohandler.vhd".
    Found 1-bit register for signal <cConv_n>.
    Found 1-bit register for signal <cSpiWordRun>.
    Found 1-bit register for signal <cDioDone>.
    Found 1-bit register for signal <cSetOutputDataDone>.
    Found 1-bit register for signal <cAutoLdRun>.
    Found 1-bit register for signal <cSetOutputDataCalled>.
    Found 4-bit register for signal <cTimer>.
    Found 32-bit register for signal <cWData>.
    Found 3-bit register for signal <cDioState>.
    Found finite state machine <FSM_55> for signal <cDioState>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 12                                             |
    | Inputs             | 6                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <cTimer[3]_GND_4983_o_add_0_OUT> created at line 1241.
    Found 1-bit 3-to-1 multiplexer for signal <cDioState[1]_GND_4983_o_Mux_20_o> created at line 100.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  42 D-type flip-flop(s).
	inferred  77 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9403DioHandler> synthesized.

Synthesizing Unit <cRio9403LdHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403ldhandler.vhd".
    Found 1-bit register for signal <cSpiWordRun>.
    Found 1-bit register for signal <cLineDirectionDone>.
    Found 1-bit register for signal <cAutoLd>.
    Found 1-bit register for signal <cAutoLdDone>.
    Found 2-bit register for signal <cModuleReqMode>.
    Found 32-bit register for signal <cLdData>.
    Found 9-bit register for signal <cTimer>.
    Found 3-bit register for signal <cLdState>.
    Found finite state machine <FSM_56> for signal <cLdState>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 14                                             |
    | Inputs             | 7                                              |
    | Outputs            | 6                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 9-bit adder for signal <cTimer[8]_GND_4985_o_add_0_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  47 D-type flip-flop(s).
	inferred  47 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9403LdHandler> synthesized.

Synthesizing Unit <cRio9403SpiWord>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9403spiword.vhd".
    Found 1-bit register for signal <cModuleSpiRun>.
    Found 1-bit register for signal <cModuleSpiCommand_HoldCs>.
    Found 1-bit register for signal <cSpiWordDone>.
    Found 8-bit register for signal <cModuleSpiDataOut>.
    Found 32-bit register for signal <cSpiRData>.
    Found 3-bit register for signal <cSpiWordState>.
    Found finite state machine <FSM_57> for signal <cSpiWordState>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 10                                             |
    | Inputs             | 2                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  43 D-type flip-flop(s).
	inferred  32 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9403SpiWord> synthesized.

Synthesizing Unit <CrioEepromRead_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crioeepromread.vhd".
    Found 1-bit register for signal <cModuleEeRun>.
    Found 1-bit register for signal <cEepromDone>.
    Found 2-bit register for signal <cModuleReqMode>.
    Found 8-bit register for signal <cEepromData>.
    Found 3-bit register for signal <cState>.
    Found finite state machine <FSM_58> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 7                                              |
    | Transitions        | 14                                             |
    | Inputs             | 5                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  12 D-type flip-flop(s).
	inferred   7 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <CrioEepromRead_2> synthesized.

Synthesizing Unit <Crio9211Resource>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211resource.vhd".
    Summary:
	no macro.
Unit <Crio9211Resource> synthesized.

Synthesizing Unit <Crio9211ResourceCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211resourcecore.vhd".
WARNING:Xst:647 - Input <clkFromResdin<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResIDSelTick<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAiDataFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <clkToResdin> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkToResIDSelTick> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <Crio9211ResourceCore> synthesized.

Synthesizing Unit <Crio9211>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211.vhd".
    Set property "IOB = TRUE" for signal <cConv_n>.
    Set property "IOB = TRUE" for signal <cIdSelOut>.
    Set property "IOB = TRUE" for signal <cSpiFunc>.
    Set property "IOB = TRUE" for signal <cSpiCs_n>.
    Set property "IOB = TRUE" for signal <cSpiClk>.
    Set property "IOB = TRUE" for signal <cSpiMosi>.
    Set property "IOB = TRUE" for signal <aIdSelIn>.
    Set property "IOB = TRUE" for signal <cEeOutputsEn>.
    Set property "IOB = TRUE" for signal <cIdSelEn>.
    Set property "IOB = TRUE" for signal <cOthersEn>.
WARNING:Xst:647 - Input <aCrioBusInOClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInTrig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInConv_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInFunc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInCs_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInMosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInSpiClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211.vhd" line 269: Output port <cStockModPresent> of the instance <cRioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211.vhd" line 269: Output port <cStockDone> of the instance <cRioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211.vhd" line 269: Output port <cStockSpiIdle> of the instance <cRioStock> is unconnected or connected to loadless signal.
    Found 1-bit register for signal <cDone_n_ms>.
    Found 1-bit register for signal <cDone_n>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
Unit <Crio9211> synthesized.

Synthesizing Unit <Crio9211EnableChainHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211enablechainhandler.vhd".
    Found 1-bit register for signal <cEepromRun>.
    Found 1-bit register for signal <cDataRun>.
    Found 1-bit register for signal <cModuleReId>.
    Found 1-bit register for signal <cSetEeEnableDone>.
    Found 1-bit register for signal <cSetDataEnableDone>.
    Found 1-bit register for signal <cInitRun>.
    Found 4-bit register for signal <cState>.
    Found finite state machine <FSM_59> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 20                                             |
    | Inputs             | 8                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforid                                      |
    | Power Up State     | waitforid                                      |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   6 D-type flip-flop(s).
	inferred  13 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9211EnableChainHandler> synthesized.

Synthesizing Unit <cRioStock_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostock.vhd".
WARNING:Xst:647 - Input <FClk80> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred   7 Multiplexer(s).
Unit <cRioStock_3> synthesized.

Synthesizing Unit <cRioStockModuleId_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockmoduleid.vhd".
    Found 1-bit register for signal <cStockEeRunMI>.
    Found 1-bit register for signal <cStockDoneMI>.
    Found 2-bit register for signal <cStockModStatusMI>.
    Found 2-bit register for signal <cStockInternalModIdStatus>.
    Found 16-bit register for signal <cStockEeAddrMI>.
    Found 33-bit register for signal <cStockErrorMI>.
    Found 3-bit register for signal <cCount>.
    Found 4-bit register for signal <cState>.
    Found 2-bit register for signal <cStockReqModeMI>.
    Found finite state machine <FSM_60> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 23                                             |
    | Inputs             | 7                                              |
    | Outputs            | 7                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | nomodulepresent                                |
    | Power Up State     | nomodulepresent                                |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit subtractor for signal <GND_5139_o_GND_5139_o_sub_19_OUT<2:0>> created at line 163.
    Found 8x57-bit Read Only RAM for signal <_n0417>
    Found 8-bit comparator equal for signal <GND_5139_o_cStockDataEE[7]_equal_23_o> created at line 162
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  60 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  10 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockModuleId_3> synthesized.

Synthesizing Unit <cRioStockSpiEngine_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockspiengine.vhd".
    Set property "IOB = TRUE" for signal <cMiso>.
    Found 1-bit register for signal <cCs_n>.
    Found 1-bit register for signal <cSpiClk>.
    Found 1-bit register for signal <cStockIdleSPI>.
    Found 1-bit register for signal <cHoldCs>.
    Found 1-bit register for signal <cSpiDone>.
    Found 1-bit register for signal <cLdDataInDly>.
    Found 12-bit register for signal <cTimer>.
    Found 4-bit register for signal <cNumBits>.
    Found 4-bit register for signal <cState>.
    Found 8-bit register for signal <cOutShiftReg>.
    Found 8-bit register for signal <cInReg>.
    Found finite state machine <FSM_61> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 25                                             |
    | Inputs             | 4                                              |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 12-bit adder for signal <cTimer[11]_GND_5141_o_add_0_OUT> created at line 1241.
    Found 12-bit subtractor for signal <GND_5141_o_GND_5141_o_sub_4_OUT<11:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_5141_o_GND_5141_o_sub_20_OUT<3:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_5141_o_GND_5141_o_sub_26_OUT<3:0>> created at line 1308.
    Found 12-bit comparator equal for signal <cTimer[11]_GND_5141_o_equal_5_o> created at line 150
INFO:Xst:2774 - HDL ADVISOR - IOB property attached to signal cMiso may hinder XST clustering optimizations.
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  38 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  26 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockSpiEngine_3> synthesized.

Synthesizing Unit <Crio9211IoHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211iohandler.vhd".
    Found 1-bit register for signal <cInitModule>.
    Found 1-bit register for signal <cConv_n>.
    Found 1-bit register for signal <cDataRdy>.
    Found 1-bit register for signal <cSpiStart>.
    Found 1-bit register for signal <cDataDone>.
    Found 1-bit register for signal <cInitDone>.
    Found 1-bit register for signal <cIoHandlerErr>.
    Found 1-bit register for signal <cEnableSpiDone>.
    Found 1-bit register for signal <cModuleSpiRun>.
    Found 3-bit register for signal <cChanNumInt>.
    Found 3-bit register for signal <cDataDoneWaitCount>.
    Found 9-bit register for signal <cTimer>.
    Found 4-bit register for signal <cNumSpiBytes>.
    Found 4-bit register for signal <cSpiByteCount>.
    Found 4-bit register for signal <cCalMemRdAddrInt>.
    Found 4-bit register for signal <cState>.
    Found 6-bit register for signal <cChanListLatched>.
    Found 8-bit register for signal <cFirstCmd>.
    Found 8-bit register for signal <cModuleSpiDataOut>.
    Found 24-bit register for signal <cConvDataInt>.
    Found 2-bit register for signal <cSpiState>.
    Found finite state machine <FSM_62> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 12                                             |
    | Transitions        | 29                                             |
    | Inputs             | 12                                             |
    | Outputs            | 20                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_63> for signal <cSpiState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 8                                              |
    | Inputs             | 4                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforrun                                     |
    | Power Up State     | sendlastbyte                                   |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 5-bit subtractor for signal <GND_5144_o_GND_5144_o_sub_105_OUT> created at line 422.
    Found 9-bit adder for signal <cTimer[8]_GND_5144_o_add_0_OUT> created at line 1241.
    Found 3-bit adder for signal <cDataDoneWaitCount[2]_GND_5144_o_add_28_OUT> created at line 1241.
    Found 3-bit adder for signal <cChanNumInt[2]_GND_5144_o_add_41_OUT> created at line 1241.
    Found 4-bit adder for signal <cCalMemRdAddrInt[2]_GND_5144_o_add_100_OUT> created at line 1241.
    Found 4-bit adder for signal <cSpiByteCount[3]_GND_5144_o_add_119_OUT> created at line 481.
    Found 4-bit adder for signal <cCalMemRdAddrInt[3]_GND_5144_o_add_121_OUT> created at line 1241.
    Found 8x4-bit Read Only RAM for signal <n0312>
    Found 4-bit 3-to-1 multiplexer for signal <cSpiState[1]_X_521_o_wide_mux_133_OUT> created at line 440.
    Found 9-bit comparator greater for signal <n0024> created at line 258
    Found 9-bit comparator greater for signal <n0029> created at line 266
    Found 3-bit comparator greater for signal <cDataDoneWaitCount[2]_GND_5144_o_LessThan_28_o> created at line 275
    Found 3-bit comparator greater for signal <cChanNumInt[2]_PWR_583_o_LessThan_91_o> created at line 401
    Found 5-bit comparator greater for signal <GND_5144_o_GND_5144_o_LessThan_106_o> created at line 422
    Found 4-bit comparator greater for signal <cSpiByteCount[3]_PWR_583_o_LessThan_114_o> created at line 471
    Found 5-bit comparator equal for signal <GND_5144_o_GND_5144_o_equal_119_o> created at line 478
    Found 4-bit comparator lessequal for signal <PWR_583_o_cSpiByteCount[3]_LessThan_121_o> created at line 484
    Summary:
	inferred   1 RAM(s).
	inferred   7 Adder/Subtractor(s).
	inferred  82 D-type flip-flop(s).
	inferred   8 Comparator(s).
	inferred  55 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <Crio9211IoHandler> synthesized.

Synthesizing Unit <Crio9211GetCalConst>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211getcalconst.vhd".
    Found 1-bit register for signal <cGetCalConstIdle>.
    Found 1-bit register for signal <cEepromRun>.
    Found 1-bit register for signal <cCalMemWrEn>.
    Found 1-bit register for signal <cClearCrc>.
    Found 1-bit register for signal <cUpdateCrc>.
    Found 1-bit register for signal <cCrcErrorBuf>.
    Found 2-bit register for signal <cModStatusOut>.
    Found 4-bit register for signal <cCountCalBytes>.
    Found 4-bit register for signal <cCalMemWrAddr>.
    Found 8-bit register for signal <cCalEepromAddrBuf>.
    Found 8-bit register for signal <cCalMemWrData>.
    Found 3-bit register for signal <cState>.
    Found finite state machine <FSM_64> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 14                                             |
    | Inputs             | 6                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waittorun                                      |
    | Power Up State     | waittorun                                      |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 4-bit adder for signal <cCountCalBytes[3]_GND_5146_o_add_15_OUT> created at line 1241.
    Found 8-bit adder for signal <cCalEepromAddrBuf[7]_GND_5146_o_add_16_OUT> created at line 1241.
    Summary:
	inferred   2 Adder/Subtractor(s).
	inferred  32 D-type flip-flop(s).
	inferred  14 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9211GetCalConst> synthesized.

Synthesizing Unit <cRio9211CalData>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9211caldata.vhd".
WARNING:Xst:647 - Input <cMultOut<35:34>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cDataRdyOut>.
    Found 2-bit register for signal <cMultInSel>.
    Found 2-bit register for signal <cState>.
    Found 42-bit register for signal <cCalibratedDataTemp>.
    Found 41-bit register for signal <cMultBuf>.
    Found finite state machine <FSM_65> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 42-bit adder for signal <cCalibratedDataTemp[-2]_cMultBuf[-2]_add_4_OUT> created at line 1584.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  86 D-type flip-flop(s).
	inferred   4 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9211CalData> synthesized.

Synthesizing Unit <cRioCalMemory_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocalmemory.vhd".
    Set property "ram_style = distributed" for signal <cCalMemData>.
WARNING:Xst:3035 - Index value(s) does not match array range for signal <cCalMemData>, simulation mismatch.
    Found 12x8-bit single-port RAM <Mram_cCalMemData> for signal <cCalMemData>.
    Summary:
	inferred   1 RAM(s).
Unit <cRioCalMemory_3> synthesized.

Synthesizing Unit <Crio9213Resource>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213resource.vhd".
    Summary:
	no macro.
Unit <Crio9213Resource> synthesized.

Synthesizing Unit <Crio9213ResourceCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213resourcecore.vhd".
WARNING:Xst:647 - Input <clkFromResdin<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResIDSelTick<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <clkToResdin> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkToResIDSelTick> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkConfigReadbackToReshold<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <Crio9213ResourceCore> synthesized.

Synthesizing Unit <Crio9213>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213.vhd".
    Set property "IOB = TRUE" for signal <cIdSelOut>.
    Set property "IOB = TRUE" for signal <cSpiFunc>.
    Set property "IOB = TRUE" for signal <cSpiCs_n>.
    Set property "IOB = TRUE" for signal <cSpiClk>.
    Set property "IOB = TRUE" for signal <cSpiMosi>.
    Set property "IOB = TRUE" for signal <cConv_n>.
    Set property "IOB = TRUE" for signal <cEeOutputsEn>.
    Set property "IOB = TRUE" for signal <cIdSelEn>.
    Set property "IOB = TRUE" for signal <cOthersEn>.
WARNING:Xst:647 - Input <cReleaseEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cReleaseEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cDataOutPortEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cDataOutPortEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cDataInPortEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cDataInPortEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cMethodPropPortOutEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cMethodPropPortOutEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cMethodPropPortInEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cMethodPropPortInEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cConfigReadbackEnableIn> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cConfigReadbackEnableClr> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInOClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInTrig> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInConv_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInFunc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInCs_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInMosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInSpiClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213.vhd" line 349: Output port <cStockModPresent> of the instance <CrioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213.vhd" line 349: Output port <cStockDone> of the instance <CrioStock> is unconnected or connected to loadless signal.
INFO:Xst:3210 - "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213.vhd" line 349: Output port <cStockSpiIdle> of the instance <CrioStock> is unconnected or connected to loadless signal.
WARNING:Xst:653 - Signal <cDataOutPortEnableOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <cMethodPropPortOutEnableOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <cMethodPropPortInEnableOut> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Found 1-bit register for signal <cDone_n>.
    Found 1-bit register for signal <cDone_n_ms>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred   9 Multiplexer(s).
Unit <Crio9213> synthesized.

Synthesizing Unit <cRioStock_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostock.vhd".
WARNING:Xst:647 - Input <FClk80> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred   7 Multiplexer(s).
Unit <cRioStock_4> synthesized.

Synthesizing Unit <cRioStockModuleId_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockmoduleid.vhd".
    Found 1-bit register for signal <cStockEeRunMI>.
    Found 1-bit register for signal <cStockDoneMI>.
    Found 2-bit register for signal <cStockModStatusMI>.
    Found 2-bit register for signal <cStockInternalModIdStatus>.
    Found 16-bit register for signal <cStockEeAddrMI>.
    Found 33-bit register for signal <cStockErrorMI>.
    Found 3-bit register for signal <cCount>.
    Found 4-bit register for signal <cState>.
    Found 2-bit register for signal <cStockReqModeMI>.
    Found finite state machine <FSM_66> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 11                                             |
    | Transitions        | 23                                             |
    | Inputs             | 7                                              |
    | Outputs            | 7                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | nomodulepresent                                |
    | Power Up State     | nomodulepresent                                |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit subtractor for signal <GND_5190_o_GND_5190_o_sub_19_OUT<2:0>> created at line 163.
    Found 8x57-bit Read Only RAM for signal <_n0417>
    Found 8-bit comparator equal for signal <GND_5190_o_cStockDataEE[7]_equal_23_o> created at line 162
    Summary:
	inferred   1 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  60 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  10 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockModuleId_4> synthesized.

Synthesizing Unit <cRioStockSpiEngine_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criostockspiengine.vhd".
    Set property "IOB = TRUE" for signal <cMiso>.
    Found 1-bit register for signal <cCs_n>.
    Found 1-bit register for signal <cSpiClk>.
    Found 1-bit register for signal <cStockIdleSPI>.
    Found 1-bit register for signal <cHoldCs>.
    Found 1-bit register for signal <cSpiDone>.
    Found 1-bit register for signal <cLdDataInDly>.
    Found 8-bit register for signal <cTimer>.
    Found 8-bit register for signal <cOutShiftReg>.
    Found 8-bit register for signal <cInReg>.
    Found 4-bit register for signal <cNumBits>.
    Found 4-bit register for signal <cState>.
    Found finite state machine <FSM_67> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 25                                             |
    | Inputs             | 5                                              |
    | Outputs            | 13                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 8-bit adder for signal <cTimer[7]_GND_5192_o_add_0_OUT> created at line 1241.
    Found 8-bit subtractor for signal <GND_5192_o_GND_5192_o_sub_4_OUT<7:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_5192_o_GND_5192_o_sub_20_OUT<3:0>> created at line 1308.
    Found 4-bit subtractor for signal <GND_5192_o_GND_5192_o_sub_26_OUT<3:0>> created at line 1308.
    Found 8-bit subtractor for signal <GND_5192_o_GND_5192_o_sub_35_OUT<7:0>> created at line 1308.
    Found 8-bit comparator equal for signal <cTimer[7]_GND_5192_o_equal_5_o> created at line 150
    Found 8-bit comparator equal for signal <cTimer[7]_GND_5192_o_equal_36_o> created at line 205
INFO:Xst:2774 - HDL ADVISOR - IOB property attached to signal cMiso may hinder XST clustering optimizations.
    Summary:
	inferred   5 Adder/Subtractor(s).
	inferred  34 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred  30 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRioStockSpiEngine_4> synthesized.

Synthesizing Unit <Crio9213EnableChainHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213enablechainhandler.vhd".
    Found 1-bit register for signal <cEepromRun>.
    Found 1-bit register for signal <cModuleReId>.
    Found 1-bit register for signal <cRequestDone>.
    Found 1-bit register for signal <cEcEePromDone>.
    Found 1-bit register for signal <cClearIoNodeWarning>.
    Found 3-bit register for signal <cTimer>.
    Found 4-bit register for signal <cState>.
    Found finite state machine <FSM_68> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 23                                             |
    | Inputs             | 9                                              |
    | Outputs            | 5                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforid                                      |
    | Power Up State     | waitforid                                      |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 3-bit adder for signal <cTimer[2]_GND_5195_o_add_0_OUT> created at line 1241.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   8 D-type flip-flop(s).
	inferred  14 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9213EnableChainHandler> synthesized.

Synthesizing Unit <cRio9213IoHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213iohandler.vhd".
    Found 1-bit register for signal <cModuleReady>.
    Found 1-bit register for signal <cUpdateStrobe>.
    Found 1-bit register for signal <cIoDone>.
    Found 1-bit register for signal <cModuleSpiRun>.
    Found 1-bit register for signal <cModuleSpiCommand_HoldCs>.
    Found 1-bit register for signal <cConfigDone>.
    Found 1-bit register for signal <cConfigRunning>.
    Found 1-bit register for signal <cTimedOut>.
    Found 1-bit register for signal <cLatchStatus>.
    Found 1-bit register for signal <cInternalConfig<5>>.
    Found 1-bit register for signal <cIoTimedOut>.
    Found 1-bit register for signal <cCommErrorSaved>.
    Found 1-bit register for signal <cCommError>.
    Found 1-bit register for signal <cClearStatusInt>.
    Found 1-bit register for signal <cDataValid>.
    Found 1-bit register for signal <cPrimed>.
    Found 1-bit register for signal <cInternalConfig<4>>.
    Found 1-bit register for signal <cInternalConfig<3>>.
    Found 1-bit register for signal <cInternalConfig<2>>.
    Found 1-bit register for signal <cInternalConfig<1>>.
    Found 1-bit register for signal <cInternalConfig<0>>.
    Found 8-bit register for signal <cModuleSpiDataOut>.
    Found 8-bit register for signal <cDataIn<3>>.
    Found 8-bit register for signal <cDataIn<2>>.
    Found 8-bit register for signal <cDataIn<1>>.
    Found 8-bit register for signal <cDataIn<0>>.
    Found 6-bit register for signal <cByteNum>.
    Found 5-bit register for signal <cChannelCounter>.
    Found 5-bit register for signal <cActivechan>.
    Found 5-bit register for signal <cStatusChan>.
    Found 19-bit register for signal <cScanlistInt>.
    Found 9-bit register for signal <cTimer>.
    Found 16-bit register for signal <cComStatusInt>.
    Found 16-bit register for signal <cTcStatusInt>.
    Found 2-bit register for signal <cIoNodeWarningInt>.
    Found 5-bit register for signal <cState>.
    Found finite state machine <FSM_69> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 17                                             |
    | Transitions        | 55                                             |
    | Inputs             | 21                                             |
    | Outputs            | 11                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idlenotready                                   |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit adder for signal <cByteNum[5]_GND_5196_o_add_48_OUT> created at line 1241.
    Found 9-bit adder for signal <cTimer[8]_GND_5196_o_add_62_OUT> created at line 1241.
    Found 5-bit adder for signal <cChannelCounter[4]_GND_5196_o_add_79_OUT> created at line 1241.
    Found 3 bit to 8 bit decoder compact to one-hot for signal <n0449> created at line 553
    Found 4 bit to 16 bit decoder compact to one-hot for signal <cStatusChan[3]_Decoder_202_OUT> created at line 627
    Found 8-bit 5-to-1 multiplexer for signal <cByteNum[2]_X_532_o_wide_mux_68_OUT> created at line 469.
    Found 1-bit 16-to-1 multiplexer for signal <cStatusChan[3]_cComStatusInt[15]_Mux_201_o> created at line 628.
    Found 1-bit 16-to-1 multiplexer for signal <cStatusChan[3]_cTcStatusInt[15]_Mux_203_o> created at line 635.
    Found 6-bit comparator not equal for signal <n0096> created at line 418
    Found 6-bit comparator lessequal for signal <cByteNum[5]_GND_5196_o_LessThan_68_o> created at line 468
    Found 6-bit comparator greater for signal <cByteNum[5]_GND_5196_o_LessThan_107_o> created at line 552
    Found 5-bit comparator lessequal for signal <cStatusChan[4]_PWR_594_o_LessThan_201_o> created at line 625
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred 144 D-type flip-flop(s).
	inferred   4 Comparator(s).
	inferred  97 Multiplexer(s).
	inferred   2 Decoder(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9213IoHandler> synthesized.

Synthesizing Unit <Crio9213GetCalConst>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213getcalconst.vhd".
    Found 1-bit register for signal <cGetCalConstIdle>.
    Found 1-bit register for signal <cEepromRun>.
    Found 1-bit register for signal <cClearCrc>.
    Found 1-bit register for signal <cUpdateCrc>.
    Found 1-bit register for signal <cCrcErrorBuf>.
    Found 1-bit register for signal <cCalMemWrEn>.
    Found 2-bit register for signal <cModStatusOut>.
    Found 2-bit register for signal <cCalMemWrAddr>.
    Found 3-bit register for signal <cCountCalBytes>.
    Found 3-bit register for signal <cCountCalWords>.
    Found 3-bit register for signal <cState>.
    Found 10-bit register for signal <cCalEepromAddrBuf>.
    Found 40-bit register for signal <cCalMemWrDataInt>.
    Found finite state machine <FSM_70> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 5                                              |
    | Transitions        | 13                                             |
    | Inputs             | 6                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waittorun                                      |
    | Power Up State     | waittorun                                      |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 10-bit adder for signal <cCalEepromAddrBuf[9]_GND_5200_o_add_18_OUT> created at line 1241.
    Found 3-bit adder for signal <cCountCalWords[2]_GND_5200_o_add_20_OUT> created at line 1241.
    Found 3-bit adder for signal <cCountCalBytes[2]_GND_5200_o_add_27_OUT> created at line 1241.
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred  66 D-type flip-flop(s).
	inferred  19 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9213GetCalConst> synthesized.

Synthesizing Unit <cRioCalMemory_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocalmemory.vhd".
    Set property "ram_style = distributed" for signal <cCalMemData>.
    Found 4x40-bit single-port RAM <Mram_cCalMemData> for signal <cCalMemData>.
    Summary:
	inferred   1 RAM(s).
Unit <cRioCalMemory_4> synthesized.

Synthesizing Unit <Crio9213FxpScaleData>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213fxpscaledata.vhd".
WARNING:Xst:647 - Input <cDataChannel<4:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cMultOut<35:28>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cComDoneLatched>.
    Found 1-bit register for signal <cComDoneOut>.
    Found 1-bit register for signal <cDataRdyOut>.
    Found 2-bit register for signal <cMultInSel>.
    Found 29-bit register for signal <cCalDataTemp>.
    Found 3-bit register for signal <cState>.
    Found 28-bit register for signal <cMultBuf>.
INFO:Xst:1799 - State latchmult10 is never reached in FSM <cState>.
INFO:Xst:1799 - State latchmult11 is never reached in FSM <cState>.
    Found finite state machine <FSM_71> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 5                                              |
    | Inputs             | 1                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 29-bit adder for signal <cCalDataTemp[-2]_cMultBuf[-2]_add_6_OUT> created at line 1584.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  62 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <Crio9213FxpScaleData> synthesized.

Synthesizing Unit <cRio9213UpdateHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9213updatehandler.vhd".
    Found 1-bit register for signal <cConv_n_out>.
    Found 1-bit register for signal <cConvertDone>.
    Found 7-bit register for signal <cCurTimeCount>.
    Found 2-bit register for signal <cState>.
    Found finite state machine <FSM_72> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 6                                              |
    | Inputs             | 3                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 7-bit adder for signal <cCurTimeCount[6]_GND_5204_o_add_0_OUT> created at line 1241.
    Found 7-bit 3-to-1 multiplexer for signal <cState[1]_X_538_o_wide_mux_9_OUT> created at line 77.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   9 D-type flip-flop(s).
	inferred   5 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9213UpdateHandler> synthesized.

Synthesizing Unit <cRio9205_Resource>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205_resource.vhd".
    Summary:
	no macro.
Unit <cRio9205_Resource> synthesized.

Synthesizing Unit <Crio9205ResourceCore>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205resourcecore.vhd".
WARNING:Xst:647 - Input <clkFromResdin<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResIDSelTick<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResClk80Mhz<2:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResClk80Mhz<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkAiDataFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkTrigFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkVoltageRangePortFromReshold<3:8>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkInputRangePortFromReshold<5:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkScanDataPortFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkReleaseFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkErrorFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:653 - Signal <clkToResdin> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkToResIDSelTick> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkToResClk80Mhz<1>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkAiDataToReshold<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkTrigToReshold<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkInputRangePortToReshold> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkScanDataPortToReshold<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkReleaseToReshold> is used but never assigned. This sourceless signal will be automatically connected to value GND.
WARNING:Xst:653 - Signal <clkErrorToReshold<0>> is used but never assigned. This sourceless signal will be automatically connected to value GND.
    Summary:
	no macro.
Unit <Crio9205ResourceCore> synthesized.

Synthesizing Unit <cRio9205>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205.vhd".
WARNING:Xst:647 - Input <cInputRangeChannel<7:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cInputRange<7:2>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInConv_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInFunc> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInCs_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInMosi> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aCrioBusInSpiClk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cTrig>.
    Found 1-bit register for signal <GenStretchCommDone.StretchBlock.cCommDoneInt>.
    Found 1-bit register for signal <cIdSelIn_ms>.
    Found 1-bit register for signal <cIdSelInPreFilter>.
    Found 1-bit register for signal <cIdSelIn>.
    Found 1-bit register for signal <cTrig_ms>.
    Found 26-bit register for signal <cScanData>.
    Found 2-bit register for signal <cIdSelFilterCount>.
    Found 2-bit adder for signal <cIdSelFilterCount[1]_GND_5236_o_add_9_OUT> created at line 912.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  34 D-type flip-flop(s).
	inferred   6 Multiplexer(s).
Unit <cRio9205> synthesized.

Synthesizing Unit <cRio9205CommSm>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205commsm.vhd".
    Set property "syn_keep = true" for signal <eDataShiftReg>.
    Set property "S = YES" for signal <eDataShiftReg>.
    Set property "buffer_type = ibuf" for signal <SsClk>.
    Set property "IOB = TRUE" for signal <cSpiCs_n>.
    Set property "IOB = TRUE" for signal <cSpiMosi>.
    Set property "IOB = TRUE" for signal <cSpiClk>.
    Set property "IOB = TRUE" for signal <cConv_n>.
    Set property "IOB = TRUE" for signal <cSsClk_ms>.
    Set property "IOBDELAY = NONE" for signal <cSsClk_ms>.
    Set property "IOB = TRUE" for signal <cMiso_ms>.
    Set property "IOBDELAY = IFD" for signal <cMiso_ms>.
WARNING:Xst:647 - Input <aDone_n> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cSpiCs_n>.
    Found 1-bit register for signal <cSpiClk>.
    Found 1-bit register for signal <cConv_n>.
    Found 1-bit register for signal <cCommDoneInt>.
    Found 1-bit register for signal <cCommRunReg>.
    Found 1-bit register for signal <cDoLastWrite>.
    Found 1-bit register for signal <cScanHist0IsDIO>.
    Found 1-bit register for signal <cScanHist1IsDIO>.
    Found 1-bit register for signal <cScanHist0IsDioInt>.
    Found 4-bit register for signal <cState>.
    Found 8-bit register for signal <cTimer>.
    Found 6-bit register for signal <cClkCount>.
    Found 16-bit register for signal <cShiftReg>.
    Found 16-bit register for signal <cScanDataInt>.
    Found 19-bit register for signal <cConvTimer>.
    Found 15-bit register for signal <eDataShiftReg>.
    Found finite state machine <FSM_73> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 15                                             |
    | Transitions        | 39                                             |
    | Inputs             | 17                                             |
    | Outputs            | 9                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 19-bit adder for signal <cConvTimer[18]_GND_5237_o_add_3_OUT> created at line 254.
    Found 6-bit adder for signal <cClkCount[5]_GND_5237_o_add_79_OUT> created at line 1241.
    Found 8-bit adder for signal <cTimer[7]_GND_5237_o_add_101_OUT> created at line 498.
    Found 8-bit comparator greater for signal <cTimer[7]_GND_5237_o_LessThan_33_o> created at line 325
    Summary:
	inferred   3 Adder/Subtractor(s).
	inferred  89 D-type flip-flop(s).
	inferred   1 Comparator(s).
	inferred  55 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9205CommSm> synthesized.

Synthesizing Unit <CrioSourceSync>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criosourcesync.vhd".
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
WARNING:Xst:37 - Detected unknown constraint/property "syn_useioff". This constraint/property is not supported by the current software release and will be ignored.
    Set property "IOB = FALSE" for signal <aMiso>.
    Set property "clock_signal = yes" for signal <SyncSpiClk>.
    Found 1-bit register for signal <oEdgeDetected_ms>.
    Found 1-bit register for signal <oEdgeDetected>.
    Found 1-bit register for signal <oEdgeDetectedDelayed>.
    Found 1-bit register for signal <oMiso_ms>.
    Found 1-bit register for signal <oMiso>.
    Found 1-bit register for signal <oShift>.
    Found 1-bit register for signal <oEdgeDetectedFE>.
    Found 1-bit register for signal <aMisoReg>.
    Found 1-bit register for signal <aEdgeDetectorOutput>.
    Summary:
	inferred   9 D-type flip-flop(s).
Unit <CrioSourceSync> synthesized.

Synthesizing Unit <cRio9205ControlSm>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205controlsm.vhd".
    Set property "INIT = POWERUP" for signal <cState>.
    Set property "IOB = TRUE" for signal <cIdSelEn>.
    Set property "IOB = TRUE" for signal <cConvEn>.
    Set property "IOB = TRUE" for signal <cIdOutputsEn>.
    Set property "IOB = TRUE" for signal <cIdSelOut>.
    Found 1-bit register for signal <cReset>.
    Found 1-bit register for signal <cIdSelOut>.
    Found 1-bit register for signal <cReset_ms>.
    Found 1-bit register for signal <cCommRun>.
    Found 1-bit register for signal <cOpDoInit>.
    Found 1-bit register for signal <cOpIoScan>.
    Found 1-bit register for signal <cIdSelEn>.
    Found 1-bit register for signal <cConvEn>.
    Found 1-bit register for signal <cIdOutputsEn>.
    Found 1-bit register for signal <cScanLineDoneInt>.
    Found 1-bit register for signal <cIoScanDoneInt>.
    Found 1-bit register for signal <cConfigDoneInt>.
    Found 1-bit register for signal <cPropertyDoneInt>.
    Found 1-bit register for signal <cEeWriteDone>.
    Found 1-bit register for signal <cIoScanHistInit>.
    Found 1-bit register for signal <cCommSmHistInit>.
    Found 1-bit register for signal <cTerminalModeWrite>.
    Found 1-bit register for signal <cInputRangeWrite>.
    Found 1-bit register for signal <cTerminalModeDone>.
    Found 1-bit register for signal <cInputRangeDone>.
    Found 1-bit register for signal <cTrigDataReady>.
    Found 1-bit register for signal <cGetCalConstRun>.
    Found 1-bit register for signal <cWriteMethodRequested>.
    Found 1-bit register for signal <cWriteMethodReqDone>.
    Found 1-bit register for signal <cWriteMethodReleaseSaved>.
    Found 1-bit register for signal <cSelfCalReInit>.
    Found 1-bit register for signal <cIncorrectMod>.
    Found 1-bit register for signal <cScanLineRunning>.
    Found 5-bit register for signal <cState>.
    Found 6-bit register for signal <cCount>.
    Found 3-bit register for signal <cCommOpInt>.
    Found 33-bit register for signal <cErrorClusterInt>.
    Found finite state machine <FSM_74> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 24                                             |
    | Transitions        | 86                                             |
    | Inputs             | 30                                             |
    | Outputs            | 14                                             |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | reset                                          |
    | Power Up State     | powerup                                        |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 6-bit adder for signal <cCount[5]_GND_5240_o_add_57_OUT> created at line 391.
    Found 8x1-bit Read Only RAM for signal <cCommOpInt[2]_GND_5240_o_Mux_85_o>
    Found 8x45-bit Read Only RAM for signal <_n1368>
    Found 6-bit comparator greater for signal <n0017> created at line 263
    Found 8-bit comparator equal for signal <n0029> created at line 307
    Summary:
	inferred   2 RAM(s).
	inferred   1 Adder/Subtractor(s).
	inferred  70 D-type flip-flop(s).
	inferred   2 Comparator(s).
	inferred 161 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9205ControlSm> synthesized.

Synthesizing Unit <cRio9205SetTriggers>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205settriggers.vhd".
    Found 1-bit register for signal <cTriggersDone>.
    Found 1-bit register for signal <cConfigRun>.
    Found 16-bit register for signal <cConfigScanLine>.
    Found 4-bit register for signal <cSetTriggersState>.
    Found finite state machine <FSM_75> for signal <cSetTriggersState>.
    -----------------------------------------------------------------------
    | States             | 9                                              |
    | Transitions        | 18                                             |
    | Inputs             | 4                                              |
    | Outputs            | 4                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  18 D-type flip-flop(s).
	inferred   8 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9205SetTriggers> synthesized.

Synthesizing Unit <cRio9205SettingRegs_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205settingregs.vhd".
    Found 2-bit register for signal <cSettingsReg<30>>.
    Found 2-bit register for signal <cSettingsReg<29>>.
    Found 2-bit register for signal <cSettingsReg<28>>.
    Found 2-bit register for signal <cSettingsReg<27>>.
    Found 2-bit register for signal <cSettingsReg<26>>.
    Found 2-bit register for signal <cSettingsReg<25>>.
    Found 2-bit register for signal <cSettingsReg<24>>.
    Found 2-bit register for signal <cSettingsReg<23>>.
    Found 2-bit register for signal <cSettingsReg<22>>.
    Found 2-bit register for signal <cSettingsReg<21>>.
    Found 2-bit register for signal <cSettingsReg<20>>.
    Found 2-bit register for signal <cSettingsReg<19>>.
    Found 2-bit register for signal <cSettingsReg<18>>.
    Found 2-bit register for signal <cSettingsReg<17>>.
    Found 2-bit register for signal <cSettingsReg<16>>.
    Found 2-bit register for signal <cSettingsReg<15>>.
    Found 2-bit register for signal <cSettingsReg<14>>.
    Found 2-bit register for signal <cSettingsReg<13>>.
    Found 2-bit register for signal <cSettingsReg<12>>.
    Found 2-bit register for signal <cSettingsReg<11>>.
    Found 2-bit register for signal <cSettingsReg<10>>.
    Found 2-bit register for signal <cSettingsReg<9>>.
    Found 2-bit register for signal <cSettingsReg<8>>.
    Found 2-bit register for signal <cSettingsReg<7>>.
    Found 2-bit register for signal <cSettingsReg<6>>.
    Found 2-bit register for signal <cSettingsReg<5>>.
    Found 2-bit register for signal <cSettingsReg<4>>.
    Found 2-bit register for signal <cSettingsReg<3>>.
    Found 2-bit register for signal <cSettingsReg<2>>.
    Found 2-bit register for signal <cSettingsReg<1>>.
    Found 2-bit register for signal <cSettingsReg<0>>.
    Found 2-bit register for signal <cSettingOut>.
    Found 2-bit register for signal <cSettingsReg<31>>.
    Found 5 bit to 32 bit decoder compact to one-hot for signal <cSettingWrChannel[4]_Decoder_0_OUT> created at line 88
    Found 2-bit 32-to-1 multiplexer for signal <cNextSettingOut> created at line 97.
    Summary:
	inferred  66 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <cRio9205SettingRegs_1> synthesized.

Synthesizing Unit <cRio9205SettingRegs_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205settingregs.vhd".
    Found 2-bit register for signal <cSettingsReg<7>>.
    Found 2-bit register for signal <cSettingsReg<6>>.
    Found 2-bit register for signal <cSettingsReg<8>>.
    Found 2-bit register for signal <cSettingsReg<30>>.
    Found 2-bit register for signal <cSettingsReg<29>>.
    Found 2-bit register for signal <cSettingsReg<28>>.
    Found 2-bit register for signal <cSettingsReg<27>>.
    Found 2-bit register for signal <cSettingsReg<26>>.
    Found 2-bit register for signal <cSettingsReg<25>>.
    Found 2-bit register for signal <cSettingsReg<24>>.
    Found 2-bit register for signal <cSettingsReg<23>>.
    Found 2-bit register for signal <cSettingsReg<22>>.
    Found 2-bit register for signal <cSettingsReg<21>>.
    Found 2-bit register for signal <cSettingsReg<20>>.
    Found 2-bit register for signal <cSettingsReg<19>>.
    Found 2-bit register for signal <cSettingsReg<18>>.
    Found 2-bit register for signal <cSettingsReg<17>>.
    Found 2-bit register for signal <cSettingsReg<16>>.
    Found 2-bit register for signal <cSettingsReg<15>>.
    Found 2-bit register for signal <cSettingsReg<14>>.
    Found 2-bit register for signal <cSettingsReg<13>>.
    Found 2-bit register for signal <cSettingsReg<12>>.
    Found 2-bit register for signal <cSettingsReg<11>>.
    Found 2-bit register for signal <cSettingsReg<10>>.
    Found 2-bit register for signal <cSettingsReg<9>>.
    Found 2-bit register for signal <cSettingsReg<5>>.
    Found 2-bit register for signal <cSettingsReg<4>>.
    Found 2-bit register for signal <cSettingsReg<3>>.
    Found 2-bit register for signal <cSettingsReg<2>>.
    Found 2-bit register for signal <cSettingsReg<1>>.
    Found 2-bit register for signal <cSettingsReg<0>>.
    Found 2-bit register for signal <cSettingOut>.
    Found 2-bit register for signal <cSettingsReg<31>>.
    Found 5 bit to 32 bit decoder compact to one-hot for signal <cSettingWrChannel[4]_Decoder_0_OUT> created at line 88
    Found 2-bit 32-to-1 multiplexer for signal <cNextSettingOut> created at line 97.
    Summary:
	inferred  66 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
	inferred   1 Decoder(s).
Unit <cRio9205SettingRegs_2> synthesized.

Synthesizing Unit <cRio9205IoHandler>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205iohandler.vhd".
    Found 1-bit register for signal <cIoScanRun>.
    Found 1-bit register for signal <cMatchHist0>.
    Found 1-bit register for signal <cMatchHist1>.
    Found 1-bit register for signal <cChannelListDone>.
    Found 7-bit register for signal <cChNumHist1>.
    Found 7-bit register for signal <cChNumHist0>.
    Found 16-bit register for signal <cScanLineHist1>.
    Found 16-bit register for signal <cScanLineHist0>.
    Found 4-bit register for signal <cState>.
    Found 6-bit register for signal <cChListIndex>.
    Found 34-bit register for signal <cChListShifter>.
    Found 2-bit register for signal <cNumChsToScan>.
    Found finite state machine <FSM_76> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 14                                             |
    | Transitions        | 29                                             |
    | Inputs             | 8                                              |
    | Outputs            | 6                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 2-bit adder for signal <cNumChsToScan[1]_GND_5246_o_add_21_OUT> created at line 238.
    Found 6-bit adder for signal <cChListIndex[5]_GND_5246_o_add_85_OUT> created at line 369.
    Found 6-bit adder for signal <cChListIndex[5]_GND_5246_o_add_87_OUT> created at line 372.
    Found 6-bit adder for signal <cChListIndex[5]_GND_5246_o_add_88_OUT> created at line 375.
    Found 16-bit comparator equal for signal <cScanLineHist1[15]_cGenScanLine[15]_equal_31_o> created at line 252
    Found 16-bit comparator equal for signal <cScanLineHist0[15]_cGenScanLine[15]_equal_33_o> created at line 254
    Found 6-bit comparator greater for signal <n0056> created at line 324
    Summary:
	inferred   4 Adder/Subtractor(s).
	inferred  92 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred  31 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9205IoHandler> synthesized.

Synthesizing Unit <cRio9205GenScanLine>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205genscanline.vhd".
    Found 32x5-bit Read Only RAM for signal <cAiBankChSel>
    Summary:
	inferred   1 RAM(s).
	inferred   3 Multiplexer(s).
Unit <cRio9205GenScanLine> synthesized.

Synthesizing Unit <cRioCalMemory_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/criocalmemory.vhd".
    Set property "ram_style = distributed" for signal <cCalMemData>.
    Found 4x47-bit single-port RAM <Mram_cCalMemData> for signal <cCalMemData>.
    Summary:
	inferred   1 RAM(s).
Unit <cRioCalMemory_5> synthesized.

Synthesizing Unit <cRio9205GetCalConst>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205getcalconst.vhd".
    Found 1-bit register for signal <cGetCalConstIdle>.
    Found 1-bit register for signal <cEePropRun>.
    Found 1-bit register for signal <cCalMemWrEn>.
    Found 1-bit register for signal <cClearCrc>.
    Found 1-bit register for signal <cUpdateCrc>.
    Found 1-bit register for signal <cCrcErrorBuf>.
    Found 3-bit register for signal <cCountCalBytes>.
    Found 4-bit register for signal <cCountCalWords>.
    Found 4-bit register for signal <cState>.
    Found 2-bit register for signal <cCountCalMem>.
    Found 2-bit register for signal <cMultInSel>.
    Found 2-bit register for signal <cCalMemWrAddr>.
    Found 9-bit register for signal <cCalEePropAddrBuf>.
    Found 32-bit register for signal <cCalDataRaw>.
    Found 36-bit register for signal <cMultBuf>.
    Found 47-bit register for signal <cCalMemWrData>.
    Found 49-bit register for signal <cAccum>.
    Found finite state machine <FSM_77> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 10                                             |
    | Transitions        | 18                                             |
    | Inputs             | 8                                              |
    | Outputs            | 6                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | waitforrun                                     |
    | Power Up State     | waitforrun                                     |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 33-bit subtractor for signal <n0150> created at line 356.
    Found 9-bit adder for signal <cCalEePropAddrBuf[8]_GND_5250_o_add_9_OUT> created at line 1241.
    Found 49-bit adder for signal <cMultBuf[30]_cAccum[47]_add_42_OUT> created at line 1548.
    Found 44-bit adder for signal <cMultBuf[25]_cAccum[42]_add_52_OUT> created at line 1548.
    Found 49-bit adder for signal <cMultBuf[13]_cAccum[47]_add_62_OUT> created at line 1548.
    Found 4-bit adder for signal <cCountCalWords[3]_GND_5250_o_add_68_OUT> created at line 1241.
    Found 2-bit adder for signal <cCountCalMem[1]_GND_5250_o_add_77_OUT> created at line 1241.
    Found 3-bit adder for signal <cCountCalBytes[2]_GND_5250_o_add_82_OUT> created at line 1241.
    Found 3-bit comparator greater for signal <cCountCalBytes[2]_GND_5250_o_LessThan_11_o> created at line 189
    Found 9-bit comparator greater for signal <n0012> created at line 192
    Found 9-bit comparator greater for signal <n0014> created at line 193
    Summary:
	inferred   8 Adder/Subtractor(s).
	inferred 192 D-type flip-flop(s).
	inferred   3 Comparator(s).
	inferred  34 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9205GetCalConst> synthesized.

Synthesizing Unit <cRio9205CalData>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio9205caldata.vhd".
WARNING:Xst:647 - Input <cMultOut<35:34>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cChanListDoneOut>.
    Found 1-bit register for signal <cChanListDoneOccurred>.
    Found 1-bit register for signal <cScanLineDoneOut>.
    Found 1-bit register for signal <cIsScanLine>.
    Found 1-bit register for signal <cIsAiRead>.
    Found 1-bit register for signal <cDataPolarity>.
    Found 1-bit register for signal <cDataRdyOut>.
    Found 2-bit register for signal <cMultCount>.
    Found 2-bit register for signal <cState>.
    Found 2-bit register for signal <cCalMemRdAddr>.
    Found 43-bit register for signal <cCalibratedDataTemp>.
    Found 7-bit register for signal <cChanNumBuf>.
    Found 42-bit register for signal <cMultBuf>.
    Found 16-bit register for signal <cCommSpiDly1>.
    Found 16-bit register for signal <cCommSpiDly2>.
    Found finite state machine <FSM_78> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 4                                              |
    | Transitions        | 6                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found 43-bit adder for signal <cCalibratedDataTemp[5]_cMultBuf[5]_add_10_OUT> created at line 1584.
    Found 43-bit subtractor for signal <cCalibratedDataTemp[5]_cOffsetBuf[0]_sub_1_OUT<42:0>> created at line 2044.
    Found 1-bit 4-to-1 multiplexer for signal <cState[1]_cIsScanLine_Mux_23_o> created at line 183.
    Found 1-bit 4-to-1 multiplexer for signal <cState[1]_cIsScanLine_Mux_24_o> created at line 183.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred 134 D-type flip-flop(s).
	inferred  19 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <cRio9205CalData> synthesized.

Synthesizing Unit <Crio80MhzClkRes>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/crio80mhzclkres.vhd".
    Set property "syn_keep = true" for signal <Clk80Mhz_out<2>>.
    Set property "syn_keep = true" for signal <Clk80Mhz_out<1>>.
    Set property "syn_keep = true" for signal <Clk80Mhz_out<0>>.
    Set property "syn_keep = true" for signal <ClkIn>.
    Set property "syn_keep = true" for signal <cKeepBit>.
    Set property "S = YES" for signal <cKeepBit>.
WARNING:Xst:647 - Input <Clk80Mhz_in<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 1-bit register for signal <cKeepBit>.
    Summary:
	inferred   1 D-type flip-flop(s).
Unit <Crio80MhzClkRes> synthesized.

Synthesizing Unit <IDSel_Timer>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/idsel_timer.vhd".
    Set property "INIT = KIDSELTICKCOUNTDELAY" for signal <cIdSelCounter>.
WARNING:Xst:647 - Input <IDSelTick_in<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Found 21-bit register for signal <cIdSelCounter>.
    Found 1-bit register for signal <IDSelTick_out<1>>.
    Found 21-bit subtractor for signal <GND_5363_o_GND_5363_o_sub_2_OUT<20:0>> created at line 69.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred  22 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <IDSel_Timer> synthesized.

Synthesizing Unit <Sleep>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/sleep.vhd".
WARNING:Xst:647 - Input <clkDinFromReshold<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <Sleep> synthesized.

Synthesizing Unit <NiFpgaArbRW_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<27:27>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<25:25>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<23:23>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<21:21>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<19:19>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<17:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<13:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<11:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<9:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_1> synthesized.

Synthesizing Unit <CustomArbForTopEnablesPortOnResTopEnablePassThru>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/customarbfortopenablesportonrestopenablepassthru.vhd".
WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000000<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000001<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000002<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000003<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000004<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000005<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000006<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000007<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000008<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000009<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder0000000A<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder0000000B<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder0000000C<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder0000000D<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder0000000E<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <CustomArbForTopEnablesPortOnResTopEnablePassThru> synthesized.

Synthesizing Unit <CustomArbForTmax_ctl_5RHFpgaReadPortOnResbushold>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/customarbfortmax_ctl_5rhfpgareadportonresbushold.vhd".
WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <CustomArbForTmax_ctl_5RHFpgaReadPortOnResbushold> synthesized.

Synthesizing Unit <NiFpgaArbRW_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<11:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<9:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_2> synthesized.

Synthesizing Unit <NiFpgaArbRW_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
    Found 1-bit register for signal <cUpdateArb>.
    Found 1-bit register for signal <cClrArb>.
    Found 2-bit register for signal <cArbEnableOut>.
    Found 2-bit register for signal <cToResHolders>.
    Found 2-bit register for signal <cState>.
    Found 2-bit register for signal <cEnableIns>.
    Found 3-bit register for signal <cToResource>.
    Found finite state machine <FSM_79> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 4                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_80> for signal <cToResource>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 30                                             |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred   8 D-type flip-flop(s).
	inferred  12 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <NiFpgaArbRW_3> synthesized.

Synthesizing Unit <NiFpgaArbSerializeAccess_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbserializeaccess.vhd".
    Found 1-bit register for signal <cFoundMatch>.
    Found 2-bit register for signal <cFoundState>.
    Found 2-bit register for signal <cState>.
    Summary:
	inferred   5 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaArbSerializeAccess_1> synthesized.

Synthesizing Unit <NiFpgaArbPowerOf2_1>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbpowerof2.vhd".
    Found 1-bit register for signal <cIntermediateEnableOut>.
    Found 1-bit register for signal <cIsPO2>.
    Found 2-bit register for signal <cOutput>.
    Found 2-bit subtractor for signal <cVecMinus1> created at line 48.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   4 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaArbPowerOf2_1> synthesized.

Synthesizing Unit <NiFpgaArbRW_4>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
    Found 1-bit register for signal <cUpdateArb>.
    Found 1-bit register for signal <cClrArb>.
    Found 3-bit register for signal <cArbEnableOut>.
    Found 3-bit register for signal <cToResHolders>.
    Found 3-bit register for signal <cToResource>.
    Found 3-bit register for signal <cEnableIns>.
    Found 2-bit register for signal <cState>.
    Found finite state machine <FSM_81> for signal <cToResource>.
    -----------------------------------------------------------------------
    | States             | 6                                              |
    | Transitions        | 30                                             |
    | Inputs             | 5                                              |
    | Outputs            | 3                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | 000                                            |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Found finite state machine <FSM_82> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 4                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  11 D-type flip-flop(s).
	inferred  17 Multiplexer(s).
	inferred   2 Finite State Machine(s).
Unit <NiFpgaArbRW_4> synthesized.

Synthesizing Unit <NiFpgaArbSerializeAccess_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbserializeaccess.vhd".
    Found 1-bit register for signal <cFoundMatch>.
    Found 3-bit register for signal <cFoundState>.
    Found 3-bit register for signal <cState>.
    Summary:
	inferred   7 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaArbSerializeAccess_2> synthesized.

Synthesizing Unit <NiFpgaArbPowerOf2_2>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbpowerof2.vhd".
    Found 1-bit register for signal <cIntermediateEnableOut>.
    Found 1-bit register for signal <cIsPO2>.
    Found 3-bit register for signal <cOutput>.
    Found 3-bit subtractor for signal <cVecMinus1> created at line 48.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   5 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaArbPowerOf2_2> synthesized.

Synthesizing Unit <NiFpgaArbRW_5>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_5> synthesized.

Synthesizing Unit <NiFpgaArbRW_6>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<35:35>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<33:33>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<31:31>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<29:29>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<27:27>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<25:25>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<23:23>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<21:21>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<19:19>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<17:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<13:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<11:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<9:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_6> synthesized.

Synthesizing Unit <CustomArbForAnsteuerung_beenden_ctl_0RHFpgaReadPortOnResbushold>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/customarbforansteuerung_beenden_ctl_0rhfpgareadportonresbushold.vhd".
WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000001<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000002<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000003<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <CustomArbForAnsteuerung_beenden_ctl_0RHFpgaReadPortOnResbushold> synthesized.

Synthesizing Unit <NiFpgaArbRW_7>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<17:17>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<13:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<11:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<9:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_7> synthesized.

Synthesizing Unit <NiFpgaArbRW_8>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_8> synthesized.

Synthesizing Unit <NiFpgaArbRW_9>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_9> synthesized.

Synthesizing Unit <NiFpgaArbRW_10>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResHolders<0:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_10> synthesized.

Synthesizing Unit <NiFpgaArbRW_11>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
    Found 1-bit register for signal <cUpdateArb>.
    Found 1-bit register for signal <cClrArb>.
    Found 2-bit register for signal <cArbEnableOut>.
    Found 2-bit register for signal <cToResHolders>.
    Found 2-bit register for signal <cState>.
    Found 2-bit register for signal <cToResource>.
    Found 2-bit register for signal <cEnableIns>.
    Found finite state machine <FSM_83> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 4                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  10 D-type flip-flop(s).
	inferred  13 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <NiFpgaArbRW_11> synthesized.

Synthesizing Unit <NiFpgaArbRW_12>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_12> synthesized.

Synthesizing Unit <NiFpgaArbRW_13>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResHolders<91:90>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<61:60>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<31:30>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_13> synthesized.

Synthesizing Unit <NiFpgaArbRW_14>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResHolders<0:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:4>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<6:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<9:10>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_14> synthesized.

Synthesizing Unit <NiFpgaArbRW_15>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
    Found 1-bit register for signal <cUpdateArb>.
    Found 1-bit register for signal <cClrArb>.
    Found 4-bit register for signal <cArbEnableOut>.
    Found 4-bit register for signal <cToResHolders>.
    Found 4-bit register for signal <cEnableIns>.
    Found 2-bit register for signal <cState>.
    Found 2-bit register for signal <cToResource>.
    Found finite state machine <FSM_84> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 4                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  16 D-type flip-flop(s).
	inferred  21 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <NiFpgaArbRW_15> synthesized.

Synthesizing Unit <NiFpgaArbSerializeAccess_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbserializeaccess.vhd".
    Found 1-bit register for signal <cFoundMatch>.
    Found 4-bit register for signal <cFoundState>.
    Found 4-bit register for signal <cState>.
    Summary:
	inferred   9 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaArbSerializeAccess_3> synthesized.

Synthesizing Unit <NiFpgaArbPowerOf2_3>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbpowerof2.vhd".
    Found 1-bit register for signal <cIntermediateEnableOut>.
    Found 1-bit register for signal <cIsPO2>.
    Found 4-bit register for signal <cOutput>.
    Found 4-bit subtractor for signal <cVecMinus1> created at line 48.
    Summary:
	inferred   1 Adder/Subtractor(s).
	inferred   6 D-type flip-flop(s).
	inferred   1 Multiplexer(s).
Unit <NiFpgaArbPowerOf2_3> synthesized.

Synthesizing Unit <NiFpgaArbRW_16>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_16> synthesized.

Synthesizing Unit <CustomArbForMiteIoLikePortOnResInterface>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/customarbformiteiolikeportonresinterface.vhd".
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	inferred   1 Multiplexer(s).
Unit <CustomArbForMiteIoLikePortOnResInterface> synthesized.

Synthesizing Unit <NiFpgaArbRW_17>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_17> synthesized.

Synthesizing Unit <NiFpgaArbRW_18>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
    Found 1-bit register for signal <cUpdateArb>.
    Found 1-bit register for signal <cClrArb>.
    Found 4-bit register for signal <cArbEnableOut>.
    Found 4-bit register for signal <cToResHolders>.
    Found 4-bit register for signal <cEnableIns>.
    Found 2-bit register for signal <cState>.
    Found 66-bit register for signal <cToResource>.
    Found finite state machine <FSM_85> for signal <cState>.
    -----------------------------------------------------------------------
    | States             | 3                                              |
    | Transitions        | 4                                              |
    | Inputs             | 2                                              |
    | Outputs            | 2                                              |
    | Clock              | Clk (rising_edge)                              |
    | Reset              | aReset (positive)                              |
    | Reset type         | asynchronous                                   |
    | Reset State        | idle                                           |
    | Power Up State     | idle                                           |
    | Encoding           | auto                                           |
    | Implementation     | LUT                                            |
    -----------------------------------------------------------------------
    Summary:
	inferred  80 D-type flip-flop(s).
	inferred  25 Multiplexer(s).
	inferred   1 Finite State Machine(s).
Unit <NiFpgaArbRW_18> synthesized.

Synthesizing Unit <NiFpgaArbRW_19>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_19> synthesized.

Synthesizing Unit <NiFpgaArbRW_20>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/nifpgaarbrw.vhd".
WARNING:Xst:647 - Input <cFromResource<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<15:15>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<13:13>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<11:11>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<9:9>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<7:7>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<5:5>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<3:3>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <cFromResHolders<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <aReset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <NiFpgaArbRW_20> synthesized.

Synthesizing Unit <CustomArbFordinPortOnResSleep>.
    Related source file is "c:/nifpga/jobs/g2k2d0o_ksw9nkc/customarbfordinportonressleep.vhd".
WARNING:Xst:647 - Input <clkFromRes<0:0>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000000<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000001<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000002<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000003<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000004<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000005<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000006<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <clkFromResholder00000007<1:1>> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <Clk> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
WARNING:Xst:647 - Input <reset> is never used. This port will be preserved and left unconnected if it belongs to a top-level block or it belongs to a sub-block and the hierarchy of this sub-block is preserved.
    Summary:
	no macro.
Unit <CustomArbFordinPortOnResSleep> synthesized.

=========================================================================
HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 29
 1024x20-bit dual-port RAM                             : 1
 12x8-bit single-port RAM                              : 3
 16384x32-bit dual-port RAM                            : 1
 16x20-bit single-port RAM                             : 1
 16x32-bit single-port RAM                             : 1
 16x35-bit single-port RAM                             : 1
 16x8-bit single-port Read Only RAM                    : 1
 32x5-bit single-port Read Only RAM                    : 1
 4x1-bit single-port Read Only RAM                     : 1
 4x2-bit single-port Read Only RAM                     : 1
 4x40-bit single-port RAM                              : 1
 4x47-bit single-port RAM                              : 1
 4x6-bit single-port Read Only RAM                     : 1
 4x66-bit single-port Read Only RAM                    : 1
 512x24-bit dual-port RAM                              : 1
 8x1-bit single-port Read Only RAM                     : 2
 8x4-bit single-port Read Only RAM                     : 3
 8x45-bit single-port Read Only RAM                    : 1
 8x57-bit single-port Read Only RAM                    : 6
# Multipliers                                          : 7
 18x18-bit multiplier                                  : 7
# Adders/Subtractors                                   : 262
 10-bit adder                                          : 3
 10-bit subtractor                                     : 5
 11-bit adder                                          : 1
 12-bit adder                                          : 5
 12-bit subtractor                                     : 6
 14-bit adder                                          : 2
 14-bit subtractor                                     : 6
 16-bit adder                                          : 4
 19-bit adder                                          : 1
 2-bit adder                                           : 13
 2-bit addsub                                          : 1
 2-bit subtractor                                      : 4
 20-bit adder                                          : 1
 21-bit subtractor                                     : 2
 25-bit adder                                          : 1
 26-bit adder                                          : 3
 26-bit subtractor                                     : 4
 27-bit adder                                          : 3
 29-bit adder                                          : 1
 3-bit adder                                           : 15
 3-bit addsub                                          : 3
 3-bit subtractor                                      : 9
 32-bit adder                                          : 21
 32-bit addsub                                         : 3
 32-bit subtractor                                     : 6
 33-bit subtractor                                     : 1
 37-bit adder                                          : 1
 37-bit addsub                                         : 1
 38-bit subtractor                                     : 1
 4-bit adder                                           : 17
 4-bit subtractor                                      : 17
 41-bit adder                                          : 2
 42-bit adder                                          : 3
 43-bit addsub                                         : 1
 44-bit adder                                          : 1
 45-bit adder                                          : 2
 49-bit adder                                          : 2
 5-bit adder                                           : 15
 5-bit subtractor                                      : 9
 54-bit adder                                          : 1
 6-bit adder                                           : 20
 6-bit subtractor                                      : 4
 7-bit adder                                           : 8
 7-bit subtractor                                      : 3
 8-bit adder                                           : 8
 8-bit addsub                                          : 1
 8-bit subtractor                                      : 8
 9-bit adder                                           : 9
 9-bit subtractor                                      : 4
# Registers                                            : 2531
 1-bit register                                        : 1804
 10-bit register                                       : 7
 1089-bit register                                     : 1
 11-bit register                                       : 1
 12-bit register                                       : 3
 14-bit register                                       : 3
 15-bit register                                       : 2
 16-bit register                                       : 22
 18-bit register                                       : 2
 19-bit register                                       : 2
 2-bit register                                        : 165
 20-bit register                                       : 8
 21-bit register                                       : 1
 24-bit register                                       : 68
 26-bit register                                       : 48
 28-bit register                                       : 1
 29-bit register                                       : 1
 3-bit register                                        : 36
 32-bit register                                       : 59
 33-bit register                                       : 44
 336-bit register                                      : 2
 34-bit register                                       : 2
 35-bit register                                       : 1
 36-bit register                                       : 13
 37-bit register                                       : 2
 384-bit register                                      : 2
 4-bit register                                        : 51
 40-bit register                                       : 1
 41-bit register                                       : 4
 416-bit register                                      : 1
 42-bit register                                       : 4
 43-bit register                                       : 1
 45-bit register                                       : 1
 47-bit register                                       : 1
 49-bit register                                       : 1
 5-bit register                                        : 22
 54-bit register                                       : 1
 6-bit register                                        : 19
 60-bit register                                       : 1
 64-bit register                                       : 6
 66-bit register                                       : 1
 7-bit register                                        : 14
 736-bit register                                      : 2
 78-bit register                                       : 3
 8-bit register                                        : 80
 800-bit register                                      : 1
 816-bit register                                      : 2
 9-bit register                                        : 10
 96-bit register                                       : 4
# Comparators                                          : 100
 10-bit comparator greater                             : 1
 12-bit comparator equal                               : 3
 13-bit comparator greater                             : 1
 13-bit comparator lessequal                           : 1
 16-bit comparator equal                               : 2
 2-bit comparator greater                              : 4
 2-bit comparator lessequal                            : 1
 3-bit comparator greater                              : 11
 3-bit comparator lessequal                            : 1
 32-bit comparator equal                               : 9
 32-bit comparator greater                             : 11
 32-bit comparator lessequal                           : 3
 4-bit comparator greater                              : 9
 4-bit comparator lessequal                            : 3
 5-bit comparator equal                                : 3
 5-bit comparator greater                              : 5
 5-bit comparator lessequal                            : 1
 6-bit comparator greater                              : 5
 6-bit comparator lessequal                            : 1
 6-bit comparator not equal                            : 1
 7-bit comparator equal                                : 1
 8-bit comparator equal                                : 13
 8-bit comparator greater                              : 1
 8-bit comparator not equal                            : 1
 9-bit comparator greater                              : 8
# Multiplexers                                         : 5859
 1-bit 16-to-1 multiplexer                             : 86
 1-bit 2-to-1 multiplexer                              : 4085
 1-bit 3-to-1 multiplexer                              : 12
 1-bit 4-to-1 multiplexer                              : 16
 10-bit 2-to-1 multiplexer                             : 23
 10-bit 3-to-1 multiplexer                             : 3
 11-bit 2-to-1 multiplexer                             : 3
 12-bit 2-to-1 multiplexer                             : 27
 14-bit 2-to-1 multiplexer                             : 7
 16-bit 2-to-1 multiplexer                             : 43
 18-bit 2-to-1 multiplexer                             : 31
 19-bit 2-to-1 multiplexer                             : 19
 2-bit 2-to-1 multiplexer                              : 136
 2-bit 3-to-1 multiplexer                              : 3
 2-bit 32-to-1 multiplexer                             : 2
 20-bit 2-to-1 multiplexer                             : 6
 21-bit 2-to-1 multiplexer                             : 2
 22-bit 2-to-1 multiplexer                             : 1
 24-bit 15-to-1 multiplexer                            : 6
 24-bit 2-to-1 multiplexer                             : 110
 25-bit 2-to-1 multiplexer                             : 4
 26-bit 2-to-1 multiplexer                             : 81
 27-bit 2-to-1 multiplexer                             : 3
 28-bit 2-to-1 multiplexer                             : 2
 29-bit 2-to-1 multiplexer                             : 2
 3-bit 2-to-1 multiplexer                              : 80
 3-bit 4-to-1 multiplexer                              : 1
 3-bit 6-to-1 multiplexer                              : 1
 32-bit 2-to-1 multiplexer                             : 74
 33-bit 2-to-1 multiplexer                             : 184
 34-bit 2-to-1 multiplexer                             : 12
 35-bit 2-to-1 multiplexer                             : 2
 36-bit 2-to-1 multiplexer                             : 11
 37-bit 2-to-1 multiplexer                             : 10
 38-bit 2-to-1 multiplexer                             : 1
 4-bit 11-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 103
 4-bit 3-to-1 multiplexer                              : 4
 4-bit 4-to-1 multiplexer                              : 1
 41-bit 2-to-1 multiplexer                             : 10
 42-bit 2-to-1 multiplexer                             : 4
 43-bit 2-to-1 multiplexer                             : 6
 44-bit 2-to-1 multiplexer                             : 1
 45-bit 2-to-1 multiplexer                             : 6
 47-bit 2-to-1 multiplexer                             : 1
 49-bit 2-to-1 multiplexer                             : 7
 5-bit 2-to-1 multiplexer                              : 148
 54-bit 2-to-1 multiplexer                             : 6
 6-bit 2-to-1 multiplexer                              : 76
 6-bit 3-to-1 multiplexer                              : 1
 64-bit 2-to-1 multiplexer                             : 4
 66-bit 2-to-1 multiplexer                             : 3
 7-bit 2-to-1 multiplexer                              : 175
 7-bit 3-to-1 multiplexer                              : 1
 78-bit 2-to-1 multiplexer                             : 3
 8-bit 2-to-1 multiplexer                              : 166
 8-bit 5-to-1 multiplexer                              : 1
 9-bit 2-to-1 multiplexer                              : 38
 96-bit 2-to-1 multiplexer                             : 4
# Logic shifters                                       : 1
 40-bit shifter logical left                           : 1
# Decoders                                             : 9
 1-of-16 decoder                                       : 1
 1-of-32 decoder                                       : 4
 1-of-8 decoder                                        : 4
# Tristates                                            : 115
 1-bit tristate buffer                                 : 115
# FSMs                                                 : 157
# Xors                                                 : 262
 1-bit xor2                                            : 220
 1-bit xor3                                            : 28
 1-bit xor4                                            : 14

=========================================================================
INFO:Xst:1767 - HDL ADVISOR - Resource sharing has identified that some arithmetic operations in this design can share the same physical resources for reduced device utilization. For improved clock frequency you may try to disable resource sharing.
WARNING:Xst:638 - in unit Crio9223ClockCrossing Conflict on KEEP property on signal cSleep and fSleep fSleep signal will be lost.
WARNING:Xst:638 - in unit Crio9223ClockCrossing Conflict on KEEP property on signal cIdSelTimerTick and fIdSelTimerTickPulse fIdSelTimerTickPulse signal will be lost.
WARNING:Xst:638 - in unit Crio80MhzClkRes Conflict on KEEP property on signal ClkIn and Clk80Mhz_out<1> Clk80Mhz_out<1> signal will be lost.
WARNING:Xst:638 - in unit Crio80MhzClkRes Conflict on KEEP property on signal N1 and Clk80Mhz_out<2> Clk80Mhz_out<2> signal will be lost.
WARNING:Xst:638 - in unit Crio80MhzClkRes Conflict on KEEP property on signal ClkIn and Clk80Mhz_out<1>1 Clk80Mhz_out<1>1 signal will be lost.
WARNING:Xst:638 - in unit Crio80MhzClkRes Conflict on KEEP property on signal Clk80Mhz_out<0> and Clk80Mhz_out<0>1 Clk80Mhz_out<0>1 signal will be lost.

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Reading core <NiLvXipFloat32Divide.ngc>.
Reading core <NiLvXipFloat32Multiply.ngc>.
Loading core <NiLvXipFloat32Divide> for timing and area information for instance <GenFloat32Divide.XilinxFloat32Divide>.
Loading core <NiLvXipFloat32Multiply> for timing and area information for instance <GenFloat32Multiply.XilinxFloat32Multiply>.
WARNING:Xst:1290 - Hierarchical block <NiFpgaFifoCountControlx> is unconnected in block <DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <NiFpgaFifoCountControlx> is unconnected in block <DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <NiFpgaFifoCountControlx> is unconnected in block <DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <Crio9223HseioReadHandlerx> is unconnected in block <Crio9220x>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <ModeSelectorPulseMask> is unconnected in block <CrioCommIntx>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <SpiPulseMask> is unconnected in block <CrioCommIntx>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_SubVICtlOrInd> is unconnected in block <n_SubVI_subMaxArray_vi_5937>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_InvisibleResholder> is unconnected in block <theVI>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_arb_rw_6> is unconnected in block <theVI>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_arb_rw_7> is unconnected in block <theVI>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_arb_rw_8> is unconnected in block <theVI>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_arb_rw_9> is unconnected in block <theVI>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <n_arb_rw_26> is unconnected in block <theVI>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <c2ResetFe_msx> is unconnected in block <BlkOut.SyncIReset>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <BlkOut.oPushToggle0_msx> is unconnected in block <HandShakeIrqAck>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <BlkRdy.iRdyPushToggle_msx> is unconnected in block <HandShakeIrqNum>.
   It will be removed from the design.
WARNING:Xst:1290 - Hierarchical block <BlkOut.oPushToggleToReadyx> is unconnected in block <HandShakeIrqNum>.
   It will be removed from the design.
WARNING:Xst:2404 -  FFs/Latches <cMultInSel<1:1>> (without init value) have a constant value of 0 in block <cRio9211CalData>.

Synthesizing (advanced) Unit <Crio9211GetCalConst>.
The following registers are absorbed into counter <cCountCalBytes>: 1 register on signal <cCountCalBytes>.
The following registers are absorbed into counter <cCalEepromAddrBuf>: 1 register on signal <cCalEepromAddrBuf>.
Unit <Crio9211GetCalConst> synthesized (advanced).

Synthesizing (advanced) Unit <Crio9211IoHandler>.
The following registers are absorbed into counter <cDataDoneWaitCount>: 1 register on signal <cDataDoneWaitCount>.
The following registers are absorbed into counter <cCalMemRdAddrInt>: 1 register on signal <cCalMemRdAddrInt>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_n0312> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 4-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cCalMemRdAddrInt> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <Crio9211IoHandler> synthesized (advanced).

Synthesizing (advanced) Unit <Crio9213GetCalConst>.
The following registers are absorbed into counter <cCountCalWords>: 1 register on signal <cCountCalWords>.
The following registers are absorbed into counter <cCalEepromAddrBuf>: 1 register on signal <cCalEepromAddrBuf>.
Unit <Crio9213GetCalConst> synthesized (advanced).

Synthesizing (advanced) Unit <Crio9264SyncResource_1>.
The following registers are absorbed into counter <cActiveChan>: 1 register on signal <cActiveChan>.
Unit <Crio9264SyncResource_1> synthesized (advanced).

Synthesizing (advanced) Unit <Crio9264SyncResource_2>.
The following registers are absorbed into counter <cActiveChan>: 1 register on signal <cActiveChan>.
Unit <Crio9264SyncResource_2> synthesized (advanced).

Synthesizing (advanced) Unit <CrioCiCartridgeIdentification>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cByteCounter[3]_X_447_o_wide_mux_4_OUT> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 8-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cByteCounter>  |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cByteCounter[2]_PWR_500_o_Mux_10_o> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 1-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cByteCounter<2:1>> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cByteCounter[3]_X_447_o_Mux_12_o> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 1-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cByteCounter<3:1>> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <CrioCiCartridgeIdentification> synthesized (advanced).

Synthesizing (advanced) Unit <CrioCiEeprom>.
The following registers are absorbed into counter <cEeWriteTimer>: 1 register on signal <cEeWriteTimer>.
Unit <CrioCiEeprom> synthesized (advanced).

Synthesizing (advanced) Unit <CrioCiModeSelectorControl>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cMode[1]_X_427_o_wide_mux_17_OUT> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 2-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cMode>         |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <CrioCiModeSelectorControl> synthesized (advanced).

Synthesizing (advanced) Unit <CrioCiPinConfig>.
The following registers are absorbed into counter <cDelayCounter>: 1 register on signal <cDelayCounter>.
The following registers are absorbed into counter <cStepNumber>: 1 register on signal <cStepNumber>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0889> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 66-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cCurrentMode>  |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <CrioCiPinConfig> synthesized (advanced).

Synthesizing (advanced) Unit <CrioCiSpiConfig>.
INFO:Xst:3217 - HDL ADVISOR - Register <cSpiDivideRate> currently described with an asynchronous reset, could be combined with distributed RAM <Mram_cSpiConfMode[1]_X_429_o_wide_mux_0_OUT> for implementation on block RAM resources if you made this reset synchronous instead.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 6-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cSpiConfMode>  |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <CrioCiSpiConfig> synthesized (advanced).

Synthesizing (advanced) Unit <DiagramReset>.
The following registers are absorbed into counter <DiagramResetFSM.rTimerCount>: 1 register on signal <DiagramResetFSM.rTimerCount>.
Unit <DiagramReset> synthesized (advanced).

Synthesizing (advanced) Unit <DmaMiteReadRegs_1>.
The following registers are absorbed into accumulator <SampleCntRegBlk.mSampleCount>: 1 register on signal <SampleCntRegBlk.mSampleCount>.
Unit <DmaMiteReadRegs_1> synthesized (advanced).

Synthesizing (advanced) Unit <DmaMiteReadRegs_2>.
The following registers are absorbed into accumulator <SampleCntRegBlk.mSampleCount>: 1 register on signal <SampleCntRegBlk.mSampleCount>.
Unit <DmaMiteReadRegs_2> synthesized (advanced).

Synthesizing (advanced) Unit <DmaMiteWriteRegs>.
The following registers are absorbed into accumulator <BlkSampleCounter.mSampleCount>: 1 register on signal <BlkSampleCounter.mSampleCount>.
The following registers are absorbed into counter <BlkSampleCounter.mDiscardCount>: 1 register on signal <BlkSampleCounter.mDiscardCount>.
Unit <DmaMiteWriteRegs> synthesized (advanced).

Synthesizing (advanced) Unit <MiteDmaInput_1>.
INFO:Xst:3226 - The RAM <NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/oDlyAddr>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 512-word x 24-bit                   |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <BrdClk>        | rise     |
    |     weA            | connected to signal <bAiWriteFifo>  | high     |
    |     addrA          | connected to signal <NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/iAddr> |          |
    |     diA            | connected to signal <bDataIn>       |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 512-word x 24-bit                   |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <MiteClk>       | rise     |
    |     addrB          | connected to signal <NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/oAddr> |          |
    |     doB            | connected to signal <NiFpgaMiteReadInterfacex/mFifoDataOut> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <MiteDmaInput_1> synthesized (advanced).

Synthesizing (advanced) Unit <MiteDmaInput_2>.
INFO:Xst:3226 - The RAM <NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/oDlyAddr>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16384-word x 32-bit                 |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <BrdClk>        | rise     |
    |     weA            | connected to signal <bAiWriteFifo>  | high     |
    |     addrA          | connected to signal <NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/iAddr> |          |
    |     diA            | connected to signal <bDataIn>       |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 16384-word x 32-bit                 |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <MiteClk>       | rise     |
    |     addrB          | connected to signal <NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/oAddr> |          |
    |     doB            | connected to signal <NiFpgaMiteReadInterfacex/mFifoDataOut> |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <MiteDmaInput_2> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaClockManagerControl>.
The following registers are absorbed into counter <rTimerCount>: 1 register on signal <rTimerCount>.
Unit <NiFpgaClockManagerControl> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaDualPortRAM_Inferred_3>.
INFO:Xst:3226 - The RAM <Mram_iRAM> will be implemented as a BLOCK RAM, absorbing the following register(s): <oLclDataOut>
    -----------------------------------------------------------------------
    | ram_type           | Block                               |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 1024-word x 20-bit                  |          |
    |     mode           | read-first                          |          |
    |     clkA           | connected to signal <IClk>          | rise     |
    |     weA            | connected to signal <iWrite>        | high     |
    |     addrA          | connected to signal <iAddr>         |          |
    |     diA            | connected to signal <iDataIn>       |          |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
    | Port B                                                              |
    |     aspect ratio   | 1024-word x 20-bit                  |          |
    |     mode           | write-first                         |          |
    |     clkB           | connected to signal <OClk>          | rise     |
    |     addrB          | connected to signal <oDlyAddr>      |          |
    |     doB            | connected to signal <oLclDataOut>   |          |
    |     dorstB         | connected to signal <oReset>        | high     |
    | reset value        | 00000000000000000000                           |
    -----------------------------------------------------------------------
    | optimization       | speed                               |          |
    -----------------------------------------------------------------------
Unit <NiFpgaDualPortRAM_Inferred_3> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaFlipFlopFifo>.
The following registers are absorbed into counter <cFullCountLoc>: 1 register on signal <cFullCountLoc>.
Unit <NiFpgaFlipFlopFifo> synthesized (advanced).

Synthesizing (advanced) Unit <NiFpgaSimpleModuloCounter>.
The following registers are absorbed into counter <cModuloCounterCount>: 1 register on signal <cModuloCounterCount>.
The following registers are absorbed into counter <cMainCounterCount>: 1 register on signal <cMainCounterCount>.
Unit <NiFpgaSimpleModuloCounter> synthesized (advanced).

Synthesizing (advanced) Unit <RegisterAccess32>.
The following registers are absorbed into counter <TimeoutManager.mCount>: 1 register on signal <TimeoutManager.mCount>.
Unit <RegisterAccess32> synthesized (advanced).

Synthesizing (advanced) Unit <TimeoutManager>.
The following registers are absorbed into counter <cCounter>: 1 register on signal <cCounter>.
Unit <TimeoutManager> synthesized (advanced).

Synthesizing (advanced) Unit <ViControl>.
The following registers are absorbed into counter <EnableInBlk.rTimerCount>: 1 register on signal <EnableInBlk.rTimerCount>.
Unit <ViControl> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9205ControlSm>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n1368> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 45-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cCount<2:0>>   |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cCommOpInt[2]_GND_5240_o_Mux_85_o> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 1-bit                      |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cCommOpInt>    |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRio9205ControlSm> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9205GenScanLine>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram_cAiBankChSel> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 32-word x 5-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <cGenAiCh>      |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to signal <cAiBankChSel>  |          |
    -----------------------------------------------------------------------
Unit <cRio9205GenScanLine> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9205GetCalConst>.
The following registers are absorbed into counter <cCountCalMem>: 1 register on signal <cCountCalMem>.
The following registers are absorbed into counter <cCalEePropAddrBuf>: 1 register on signal <cCalEePropAddrBuf>.
Unit <cRio9205GetCalConst> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9205IoHandler>.
The following registers are absorbed into counter <cNumChsToScan>: 1 register on signal <cNumChsToScan>.
Unit <cRio9205IoHandler> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9264CalData>.
INFO:Xst:3216 - HDL ADVISOR - LUT implementation is currently selected for the RAM <Mram_cList>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 20-bit                    |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <cWriteMem>     | high     |
    |     addrA          | connected to signal <cCalMemAddr>   |          |
    |     diA            | connected to signal <cAoDataIn>     |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRio9264CalData> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9264CalReciprocal>.
The following registers are absorbed into counter <cIterCount>: 1 register on signal <cIterCount>.
Unit <cRio9264CalReciprocal> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9264GetCalConst>.
The following registers are absorbed into counter <cCountCalWords>: 1 register on signal <cCountCalWords>.
The following registers are absorbed into counter <cCalEePropAddrBuf>: 1 register on signal <cCalEePropAddrBuf>.
Unit <cRio9264GetCalConst> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9264IoHandler>.
The following registers are absorbed into counter <cInitChannel>: 1 register on signal <cInitChannel>.
Unit <cRio9264IoHandler> synthesized (advanced).

Synthesizing (advanced) Unit <cRio9403DioHandler>.
The following registers are absorbed into counter <cTimer>: 1 register on signal <cTimer>.
Unit <cRio9403DioHandler> synthesized (advanced).

Synthesizing (advanced) Unit <cRioCalMemory_1>.
INFO:Xst:3216 - HDL ADVISOR - LUT implementation is currently selected for the RAM <Mram_cCalMemData>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 35-bit                    |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <cCalMemWrEn>   | high     |
    |     addrA          | connected to signal <cCalMemAddr>   |          |
    |     diA            | connected to signal <cCalMemWrData> |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioCalMemory_1> synthesized (advanced).

Synthesizing (advanced) Unit <cRioCalMemory_2>.
INFO:Xst:3216 - HDL ADVISOR - LUT implementation is currently selected for the RAM <Mram_cCalMemData>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 16-word x 32-bit                    |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <cCalMemWrEn>   | high     |
    |     addrA          | connected to signal <cCalMemAddr>   |          |
    |     diA            | connected to signal <cCalMemWrData> |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioCalMemory_2> synthesized (advanced).

Synthesizing (advanced) Unit <cRioCalMemory_3>.
INFO:Xst:3216 - HDL ADVISOR - LUT implementation is currently selected for the RAM <Mram_cCalMemData>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 12-word x 8-bit                     |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <cCalMemWrEn>   | high     |
    |     addrA          | connected to signal <cCalMemAddr>   |          |
    |     diA            | connected to signal <cCalMemWrData> |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioCalMemory_3> synthesized (advanced).

Synthesizing (advanced) Unit <cRioCalMemory_4>.
INFO:Xst:3216 - HDL ADVISOR - LUT implementation is currently selected for the RAM <Mram_cCalMemData>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 40-bit                     |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <cCalMemWrEn>   | high     |
    |     addrA          | connected to signal <cCalMemAddr>   |          |
    |     diA            | connected to signal <cCalMemWrData> |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioCalMemory_4> synthesized (advanced).

Synthesizing (advanced) Unit <cRioCalMemory_5>.
INFO:Xst:3216 - HDL ADVISOR - LUT implementation is currently selected for the RAM <Mram_cCalMemData>. If you want the register to be removed and the RAM to be implemented as block RAM, please change the RAM implementation style accordingly.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 4-word x 47-bit                     |          |
    |     clkA           | connected to signal <Clk>           | rise     |
    |     weA            | connected to signal <cCalMemWrEn>   | high     |
    |     addrA          | connected to signal <cCalMemAddr>   |          |
    |     diA            | connected to signal <cCalMemWrData> |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioCalMemory_5> synthesized (advanced).

Synthesizing (advanced) Unit <cRioCalMultiply>.
	Found pipelined multiplier on signal <cMultIn1[17]_cMultIn2[17]_MuLt_0_OUT>:
		- 1 pipeline level(s) found in a register connected to the multiplier macro output.
		Pushing register(s) into the multiplier macro.
INFO:Xst:2385 - HDL ADVISOR - You can improve the performance of the multiplier Mmult_cMultIn1[17]_cMultIn2[17]_MuLt_0_OUT by adding 1 register level(s).
Unit <cRioCalMultiply> synthesized (advanced).

Synthesizing (advanced) Unit <cRioStockModeSelector>.
The following registers are absorbed into counter <cIdSelFilterCount>: 1 register on signal <cIdSelFilterCount>.
Unit <cRioStockModeSelector> synthesized (advanced).

Synthesizing (advanced) Unit <cRioStockModuleId_1>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0418> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 57-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <GND_4694_o_GND_4694_o_sub_19_OUT> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioStockModuleId_1> synthesized (advanced).

Synthesizing (advanced) Unit <cRioStockModuleId_2>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0418> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 57-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <GND_4977_o_GND_4977_o_sub_19_OUT> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioStockModuleId_2> synthesized (advanced).

Synthesizing (advanced) Unit <cRioStockModuleId_3>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0417> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 57-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <GND_5139_o_GND_5139_o_sub_19_OUT> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioStockModuleId_3> synthesized (advanced).

Synthesizing (advanced) Unit <cRioStockModuleId_4>.
INFO:Xst:3218 - HDL ADVISOR - The RAM <Mram__n0417> will be implemented on LUTs either because you have described an asynchronous read or because of currently unsupported block RAM features. If you have described an asynchronous read, making it synchronous would allow you to take advantage of available block RAM resources, for optimized device usage and improved timings. Please refer to your documentation for coding guidelines.
    -----------------------------------------------------------------------
    | ram_type           | Distributed                         |          |
    -----------------------------------------------------------------------
    | Port A                                                              |
    |     aspect ratio   | 8-word x 57-bit                     |          |
    |     weA            | connected to signal <GND>           | high     |
    |     addrA          | connected to signal <GND_5190_o_GND_5190_o_sub_19_OUT> |          |
    |     diA            | connected to signal <GND>           |          |
    |     doA            | connected to internal node          |          |
    -----------------------------------------------------------------------
Unit <cRioStockModuleId_4> synthesized (advanced).

Synthesizing (advanced) Unit <whileloop>.
The following registers are absorbed into counter <lp_iteration>: 1 register on signal <lp_iteration>.
Unit <whileloop> synthesized (advanced).

=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# RAMs                                                 : 29
 1024x20-bit dual-port block RAM                       : 1
 12x8-bit single-port distributed RAM                  : 3
 16384x32-bit dual-port block RAM                      : 1
 16x20-bit single-port distributed RAM                 : 1
 16x32-bit single-port distributed RAM                 : 1
 16x35-bit single-port distributed RAM                 : 1
 16x8-bit single-port distributed Read Only RAM        : 1
 32x5-bit single-port distributed Read Only RAM        : 1
 4x1-bit single-port distributed Read Only RAM         : 1
 4x2-bit single-port distributed Read Only RAM         : 1
 4x40-bit single-port distributed RAM                  : 1
 4x47-bit single-port distributed RAM                  : 1
 4x6-bit single-port distributed Read Only RAM         : 1
 4x66-bit single-port distributed Read Only RAM        : 1
 512x24-bit dual-port block RAM                        : 1
 8x1-bit single-port distributed Read Only RAM         : 2
 8x4-bit single-port distributed Read Only RAM         : 3
 8x45-bit single-port distributed Read Only RAM        : 1
 8x57-bit single-port distributed Read Only RAM        : 6
# Multipliers                                          : 7
 18x18-bit registered multiplier                       : 7
# Adders/Subtractors                                   : 201
 1-bit subtractor                                      : 1
 10-bit adder                                          : 2
 10-bit subtractor                                     : 1
 10-bit subtractor borrow in                           : 1
 11-bit adder                                          : 1
 12-bit adder                                          : 3
 12-bit subtractor                                     : 6
 13-bit subtractor                                     : 3
 14-bit adder                                          : 2
 14-bit subtractor                                     : 1
 14-bit subtractor borrow in                           : 1
 19-bit adder                                          : 2
 2-bit adder                                           : 3
 2-bit addsub                                          : 1
 2-bit subtractor                                      : 3
 21-bit subtractor                                     : 2
 25-bit adder                                          : 4
 25-bit subtractor                                     : 4
 27-bit adder                                          : 3
 29-bit adder                                          : 1
 3-bit adder                                           : 11
 3-bit addsub                                          : 2
 3-bit subtractor                                      : 9
 32-bit adder                                          : 14
 32-bit subtractor                                     : 4
 37-bit adder                                          : 1
 37-bit addsub                                         : 1
 38-bit subtractor                                     : 1
 4-bit adder                                           : 14
 4-bit subtractor                                      : 17
 41-bit adder                                          : 2
 42-bit adder                                          : 3
 43-bit addsub                                         : 1
 44-bit adder                                          : 1
 45-bit adder                                          : 2
 49-bit adder                                          : 2
 5-bit adder                                           : 8
 5-bit subtractor                                      : 6
 5-bit subtractor borrow in                            : 1
 54-bit adder                                          : 1
 6-bit adder                                           : 15
 6-bit subtractor                                      : 2
 7-bit adder                                           : 8
 7-bit subtractor                                      : 3
 8-bit adder                                           : 7
 8-bit addsub                                          : 1
 8-bit subtractor                                      : 8
 9-bit adder                                           : 7
 9-bit subtractor                                      : 3
 9-bit subtractor borrow in                            : 1
# Counters                                             : 54
 10-bit down counter                                   : 1
 10-bit up counter                                     : 1
 16-bit up counter                                     : 4
 2-bit up counter                                      : 10
 3-bit up counter                                      : 4
 3-bit updown counter                                  : 1
 32-bit down counter                                   : 3
 32-bit up counter                                     : 7
 4-bit down counter                                    : 1
 4-bit up counter                                      : 7
 5-bit down counter                                    : 2
 5-bit up counter                                      : 6
 6-bit down counter                                    : 1
 6-bit up counter                                      : 1
 8-bit up counter                                      : 3
 9-bit up counter                                      : 2
# Accumulators                                         : 3
 32-bit updown loadable accumulator                    : 3
# Registers                                            : 19534
 Flip-Flops                                            : 19534
# Comparators                                          : 100
 10-bit comparator greater                             : 1
 12-bit comparator equal                               : 3
 13-bit comparator greater                             : 1
 13-bit comparator lessequal                           : 1
 16-bit comparator equal                               : 2
 2-bit comparator greater                              : 4
 2-bit comparator lessequal                            : 1
 3-bit comparator greater                              : 11
 3-bit comparator lessequal                            : 1
 32-bit comparator equal                               : 9
 32-bit comparator greater                             : 11
 32-bit comparator lessequal                           : 3
 4-bit comparator greater                              : 9
 4-bit comparator lessequal                            : 3
 5-bit comparator equal                                : 3
 5-bit comparator greater                              : 5
 5-bit comparator lessequal                            : 1
 6-bit comparator greater                              : 5
 6-bit comparator lessequal                            : 1
 6-bit comparator not equal                            : 1
 7-bit comparator equal                                : 1
 8-bit comparator equal                                : 13
 8-bit comparator greater                              : 1
 8-bit comparator not equal                            : 1
 9-bit comparator greater                              : 8
# Multiplexers                                         : 6760
 1-bit 16-to-1 multiplexer                             : 86
 1-bit 2-to-1 multiplexer                              : 5074
 1-bit 3-to-1 multiplexer                              : 12
 1-bit 4-to-1 multiplexer                              : 16
 10-bit 2-to-1 multiplexer                             : 21
 10-bit 3-to-1 multiplexer                             : 3
 11-bit 2-to-1 multiplexer                             : 3
 12-bit 2-to-1 multiplexer                             : 27
 14-bit 2-to-1 multiplexer                             : 7
 16-bit 2-to-1 multiplexer                             : 39
 18-bit 2-to-1 multiplexer                             : 31
 19-bit 2-to-1 multiplexer                             : 19
 2-bit 2-to-1 multiplexer                              : 114
 2-bit 3-to-1 multiplexer                              : 3
 2-bit 32-to-1 multiplexer                             : 2
 20-bit 2-to-1 multiplexer                             : 6
 21-bit 2-to-1 multiplexer                             : 2
 22-bit 2-to-1 multiplexer                             : 1
 24-bit 15-to-1 multiplexer                            : 6
 24-bit 2-to-1 multiplexer                             : 109
 25-bit 2-to-1 multiplexer                             : 4
 26-bit 2-to-1 multiplexer                             : 78
 27-bit 2-to-1 multiplexer                             : 3
 28-bit 2-to-1 multiplexer                             : 2
 29-bit 2-to-1 multiplexer                             : 2
 3-bit 2-to-1 multiplexer                              : 75
 3-bit 4-to-1 multiplexer                              : 1
 3-bit 6-to-1 multiplexer                              : 1
 32-bit 2-to-1 multiplexer                             : 66
 33-bit 2-to-1 multiplexer                             : 184
 34-bit 2-to-1 multiplexer                             : 12
 35-bit 2-to-1 multiplexer                             : 1
 36-bit 2-to-1 multiplexer                             : 11
 37-bit 2-to-1 multiplexer                             : 10
 38-bit 2-to-1 multiplexer                             : 1
 4-bit 11-to-1 multiplexer                             : 1
 4-bit 2-to-1 multiplexer                              : 95
 4-bit 3-to-1 multiplexer                              : 4
 4-bit 4-to-1 multiplexer                              : 1
 41-bit 2-to-1 multiplexer                             : 10
 42-bit 2-to-1 multiplexer                             : 4
 43-bit 2-to-1 multiplexer                             : 6
 44-bit 2-to-1 multiplexer                             : 1
 45-bit 2-to-1 multiplexer                             : 6
 49-bit 2-to-1 multiplexer                             : 7
 5-bit 2-to-1 multiplexer                              : 140
 54-bit 2-to-1 multiplexer                             : 5
 6-bit 2-to-1 multiplexer                              : 74
 6-bit 3-to-1 multiplexer                              : 1
 64-bit 2-to-1 multiplexer                             : 4
 66-bit 2-to-1 multiplexer                             : 2
 7-bit 2-to-1 multiplexer                              : 174
 7-bit 3-to-1 multiplexer                              : 1
 8-bit 2-to-1 multiplexer                              : 155
 8-bit 5-to-1 multiplexer                              : 1
 9-bit 2-to-1 multiplexer                              : 36
# Logic shifters                                       : 1
 40-bit shifter logical left                           : 1
# Decoders                                             : 9
 1-of-16 decoder                                       : 1
 1-of-32 decoder                                       : 4
 1-of-8 decoder                                        : 4
# FSMs                                                 : 157
# Xors                                                 : 262
 1-bit xor2                                            : 220
 1-bit xor3                                            : 28
 1-bit xor4                                            : 14

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================
WARNING:Xst:1303 - From in and out of unit Miso.MisoMux, both signals Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> and SpiClk.SpiClkMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> have a KEEP attribute, signal Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> will be lost.
WARNING:Xst:1303 - From in and out of unit Func.FuncMux, both signals Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> and SpiClk.SpiClkMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> have a KEEP attribute, signal Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> will be lost.
WARNING:Xst:1303 - From in and out of unit Done_n.Done_nMux, both signals Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> and SpiClk.SpiClkMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> have a KEEP attribute, signal Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> will be lost.
WARNING:Xst:1303 - From in and out of unit Trig.TrigMux, both signals Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> and SpiClk.SpiClkMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> have a KEEP attribute, signal Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> will be lost.
WARNING:Xst:1303 - From in and out of unit OClk.OClkMux, both signals Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> and SpiClk.SpiClkMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> have a KEEP attribute, signal Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<1> will be lost.
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/RegisterAccessx/RegisterAccess32x/FSM_13> on signal <ReadBlk.mReadState[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 reading | 01
 done    | 10
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/RegisterAccessx/RegisterAccess32x/FSM_12> on signal <WriteBlk.mWriteState[1:2]> with user encoding.
-------------------------
 State       | Encoding
-------------------------
 idle        | 00
 writing     | 01
 writingwait | 10
 done        | 11
-------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkDmaDisabler.DmaDisablerx/FSM_16> on signal <mState[1:3]> with one-hot encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkDmaDisabler.DmaDisablerx/FSM_16> on signal <mState[1:3]> with one-hot encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkDmaDisabler.DmaDisablerx/FSM_16> on signal <mState[1:3]> with one-hot encoding.
-----------------------
 State     | Encoding
-----------------------
 disabled  | 001
 disabling | 100
 enabled   | 010
-----------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkCDRd.CpuDataRdx/FSM_17> on signal <mState[1:4]> with user encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkCDRd.CpuDataRdx/FSM_17> on signal <mState[1:4]> with user encoding.
-------------------------------------
 State                   | Encoding
-------------------------------------
 idle                    | 0000
 burst1                  | 0001
 checkformiteburstdenial | 0010
 burst2                  | 0011
 burst3                  | 0100
 single1                 | 0101
 single2                 | 0110
 single3                 | 0111
 single4                 | 1000
-------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/FSM_14> on signal <pTimeoutState[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 waiting | 01
 done    | 10
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/FSM_15> on signal <cDisablerState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 wait4disabledone   | 001
 wait4resetdone     | 010
 wait4pushresetdone | 011
 wait4popresetdone  | 100
 wait4reenable      | 101
 wait4empty         | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/FSM_18> on signal <pTimeoutState[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 waiting | 01
 done    | 10
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/FSM_15> on signal <cDisablerState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 wait4disabledone   | 001
 wait4resetdone     | 010
 wait4pushresetdone | 011
 wait4popresetdone  | 100
 wait4reenable      | 101
 wait4empty         | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkHostRegs.DmaMiteWriteRegsx/FSM_22> on signal <BlkSampleCounter.mErrorState[1:3]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 idle              | 000
 abletotransfer    | 001
 erroroccurred     | 010
 errordetected     | 011
 datashifted       | 100
 discardingbaddata | 101
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFifo.BlkCDWr.CpuDataWrx/FSM_21> on signal <mState[1:4]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 0000
 burst0  | 0001
 burst1  | 0010
 burst2  | 0011
 burst3  | 0100
 single1 | 0101
 single2 | 0110
 single3 | 0111
 single4 | 1000
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/FSM_19> on signal <pTimeoutState[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 waiting | 01
 done    | 10
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Output.FifoClearController/FSM_20> on signal <cDisablerState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 wait4disabledone   | 001
 wait4resetdone     | 010
 wait4pushresetdone | 011
 wait4popresetdone  | 100
 wait4reenable      | 101
 wait4empty         | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/Crio9223EnableChainHandlerx/FSM_26> on signal <cState[1:4]> with user encoding.
--------------------------------------
 State                    | Encoding
--------------------------------------
 idle                     | 0000
 waitforionoderequestdone | 0001
 waitforionodecomplete    | 0010
 sendionodedone           | 0011
 waitforionoderelease     | 0100
 waitforeepromdone        | 0101
 nextidle                 | 0110
 waitforhseio             | 0111
 hseioidle                | 1000
--------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/IoNodeRequestEnableChainSMx/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/EepromEnableChainSMx/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/HseioResetEnableChainSMx/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/RequestEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/EepromEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/DioEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/EEPropertyEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/SetOutputDataEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/LineDirectionEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/DataEnableChain/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/DataEnableChain/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/DataEnableChain/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/EepromEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/EepromEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/EepromEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/RequestEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/EepromEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/RequestEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/ChannelListEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/TerminalModeEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/InputRangeEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/TriggersEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/ScanLineEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/PropertyEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/EeWriteEnableChainSM/FSM_25> on signal <cState[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 running | 01
 cleared | 10
 done    | 11
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/Crio9223IoHandlerx/FSM_27> on signal <cState[1:3]> with user encoding.
--------------------------------------
 State                    | Encoding
--------------------------------------
 idle                     | 000
 waitforconvpulsecomplete | 001
 waitforsampledatavalid   | 010
 waitforrelease           | 011
 waitforminsampletime     | 100
--------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/Crio9220Initializerx/Crio9220GetCalConstx/FSM_28> on signal <cState[1:4]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 idle            | 0000
 savecalconst    | 0001
 waitforcalconst | 0010
 latchmult00     | 0011
 latchmult01     | 0100
 latchmult10     | 0101
 latchmult11     | 0110
 donemult        | 0111
 getnextcalconst | 1000
 checkcrcresult  | 1001
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/Crio9220CalDatax/FSM_29> on signal <cState[1:3]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 000
 latchmult0 | 001
 latchmult1 | 010
 donemult   | 011
 update     | 100
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/Crio9223SampleSerializerx/FSM_30> on signal <cState[1:2]> with user encoding.
-------------------------------------
 State                   | Encoding
-------------------------------------
 waitforhsiinputwritereq | 00
 waitforfirstsamplecal   | 01
 waitforsecondsamplecal  | 10
-------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiModeSelectorControlx/FSM_31> on signal <cState[1:4]> with user encoding.
-----------------------------------------
 State                       | Encoding
-----------------------------------------
 waitfordefaultpinconfigdone | 0000
 waitfordefaultspiconfigdone | 0001
 waitformoderequest          | 0010
 waitforpinconfigdone        | 0011
 waitforspiconfigdone        | 0100
 waitformoderelease          | 0101
 waitforidlepinconfig        | 0110
 waitforidlespiconfig        | 0111
 waitforwakeuporinsertion    | 1000
 disablespireq               | 1001
 disablehsireq               | 1010
 enablehsireq                | 1011
 disablespirel               | 1100
 disablehsirel               | 1101
 enablehsirel                | 1110
 disablehsiidle              | 1111
-----------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/FSM_32> on signal <cState[1:3]> with user encoding.
----------------------------
 State          | Encoding
----------------------------
 waitforrun     | 000
 microstep1     | 001
 microstep2     | 010
 delay          | 011
 updateoeonly   | unreached
 waitforcartdet | 101
----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiEepromx/FSM_33> on signal <cDataValidMaskState[1:2]> with user encoding.
-------------------------------------
 State                   | Encoding
-------------------------------------
 waitforrun              | 00
 maskthreedatavalids     | 01
 waitforendoftransaction | 10
 maskalldatavalids       | 11
-------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiEepromx/FSM_34> on signal <cState[1:5]> with user encoding.
-------------------------------------
 State                   | Encoding
-------------------------------------
 waitforrun              | 00000
 waitforgranted          | 00001
 sendreadcommand         | 00010
 readcommandack          | 00011
 firstaddrbyteack        | 00100
 sendfirstaddrbyte       | 00101
 sendsecondaddrbyte      | 00110
 readanotherbyte         | 00111
 waitforlastbyte         | 01000
 waitforreleased         | 01001
 waitfornotqueued        | 01010
 waitforcommandack       | 01011
 sendwriteenablecommand  | 01100
 sendwritecommand        | 01101
 writecommandack         | 01110
 sendfirstwriteaddrbyte  | 01111
 firstwriteaddrbyteack   | 10000
 sendsecondwriteaddrbyte | 10001
 secondwriteaddrbyteack  | 10010
 sendwritedatabyte       | 10011
 finishwritecommand      | 10100
 sendreadstatuscommand   | 10101
 readstatuscommandack    | 10110
 checkwritestatus        | 10111
-------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiCartridgeIdentificationx/FSM_35> on signal <cState[1:2]> with gray encoding.
-------------------------------
 State             | Encoding
-------------------------------
 waitforrun        | 00
 sendreadcommand   | 01
 readbytes         | 11
 waitforeepromdone | 10
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiInitSequencex/FSM_36> on signal <cState[1:4]> with user encoding.
--------------------------------------------
 State                          | Encoding
--------------------------------------------
 waitforpbinit                  | 0000
 waitformodulepowerup           | 0001
 waitforid                      | 0010
 waitforinit                    | 0011
 waitfordefaultmode             | 0100
 nomodule                       | 0101
 wrongmodule                    | 0110
 checkifeeprombusyforinit       | 0111
 revertdefaultmodeafterinitfail | 1000
 initfailed                     | 1001
 avoidinitracecondition         | 1010
 avoididracecondition           | 1011
 checkifeeprombusyforid         | 1100
 success                        | 1101
 sleeping                       | 1110
--------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/FSM_42> on signal <cState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 seteerun           | 001
 waitforeedone      | 010
 setenablechaindone | 011
 nexteerun          | 100
 nextsetdone        | 101
 nextidle           | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRio9264CalData/FSM_48> on signal <cState[1:3]> with user encoding.
-------------------------
 State       | Encoding
-------------------------
 idle        | 000
 primemult   | 001
 latchmult00 | 010
 latchmult01 | 011
 latchmult10 | 100
 latchmult11 | 101
 donemult    | 110
 suboffset   | 111
-------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRio9264IoHandler/FSM_43> on signal <cState[1:4]> with user encoding.
---------------------------
 State         | Encoding
---------------------------
 idle          | 0000
 byte2         | 0001
 byte1         | 0010
 byte0         | 0011
 spiwritedelay | 0100
 initmodule    | 0101
 spiquiettime  | 0110
 idlenotready  | 0111
 waitfordata   | 1000
---------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/FSM_38> on signal <cState[1:4]> with user encoding.
------------------------------------------------
 State                              | Encoding
------------------------------------------------
 reset                              | 0000
 deb0                               | 0001
 deb1                               | 0010
 modulepresent                      | 0011
 nomodule                           | 0100
 modknownidsel1func1                | 0101
 modknownidsel1func0                | 0110
 modknownidsel0func0                | 0111
 modknownidsel0func1                | 1000
 drvidsellow                        | 1001
 eneerdlines                        | 1010
 eemode                             | 1011
 exiteemode                         | 1100
 exiteewaitidsel                    | 1101
 waitaftereetocheckformoduleremoval | 1110
------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/FSM_40> on signal <cState[1:3]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 idle            | 000
 sendreadcommand | 001
 sendaddrmsb     | 010
 sendaddrlsb     | 011
 getdata         | 100
 setdonesignal   | 101
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModuleIdSm/FSM_37> on signal <cState[1:4]> with user encoding.
---------------------------------
 State               | Encoding
---------------------------------
 nomodulepresent     | 0000
 idle                | 0001
 settoeemode         | 0010
 waitforeeread       | 0011
 correctdatareceived | 0100
 waitformsnoterror   | 0101
 waitformserror      | 0110
 moduleerror         | 0111
 nextmsnoterror      | 1000
 nexteemode          | 1001
 nextmserror         | 1010
---------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/SpiEngine/FSM_39> on signal <cState[1:4]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 idle              | 0000
 waitforcs         | 0001
 waitforspiclkhigh | 0010
 waitforspiclklow  | 0011
 holdcs            | 0100
 setdonereleasecs  | 0101
 setdoneholdcs     | 0110
 releasecs         | 0111
 waitforcshigh     | 1000
 waitandrun        | 1001
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRio9264EnableChainHandler/FSM_41> on signal <cState[1:4]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 waitforid         | 0000
 incorrectmodule   | 0001
 reid              | 0010
 waitforeepromdone | 0011
 idle              | 0100
 eeprom            | 0101
 aorequested       | 0110
 nextidlenoerror   | 0111
 nextwaitforid     | 1000
 convwaitruneenext | 1001
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRio9264UpdateHandler/FSM_44> on signal <cState[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 update     | 01
 updatewait | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRio9264GetCalConst/FSM_45> on signal <cState[1:4]> with user encoding.
----------------------------------
 State                | Encoding
----------------------------------
 waittorungetcalconst | 0000
 savecalconst         | 0001
 waitforcalconst      | 0010
 latchmult00          | 0011
 latchmult10          | 0100
 latchmult01          | 0101
 latchmult11          | 0110
 donemult             | 0111
 idle                 | 1000
 waitforfirstmult     | 1001
 checkcrcresult       | 1010
 recipwait            | 1011
----------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRio9264GetCalConst/GenGetCalConst.cRio9264CalReciprocalx/FSM_46> on signal <cState[1:3]> with user encoding.
------------------------------
 State            | Encoding
------------------------------
 idle             | 000
 waitforfirstmult | 001
 latchmult00      | 010
 latchmult01      | 011
 latchmult10      | 100
 latchmult11      | 101
 donemult         | 110
 setupnextmult    | 111
------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRio9264GetCalConst/GenGetCalConst.cRio9264CalReciprocalx/FSM_47> on signal <cCalcStage[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 notstarted | 00
 first      | 01
 second     | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRio9403CommHandler/cRio9403DioHandler/FSM_55> on signal <cDioState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 spiwordrun         | 001
 waitforspiworddone | 010
 diodone            | 011
 waitforlddone      | 100
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRio9403CommHandler/cRio9403LdHandler/FSM_56> on signal <cLdState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 nextspiwordrun     | 001
 spiwordrun         | 010
 waitforspiworddone | 011
 nextlddone         | 100
 lddone             | 101
 waitforreconfig    | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRio9403CommHandler/CrioEepromRead/FSM_58> on signal <cState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 seteerun           | 001
 waitforeedone      | 010
 setenablechaindone | 011
 nexteerun          | 100
 nextsetdone        | 101
 nextidle           | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRio9403CommHandler/cRio9403SpiWord/FSM_57> on signal <cSpiWordState[1:3]> with user encoding.
------------------------------
 State            | Encoding
------------------------------
 idle             | 000
 transactionbyte3 | 001
 transactionbyte2 | 010
 transactionbyte1 | 011
 transactionbyte0 | 100
------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/FSM_38> on signal <cState[1:4]> with user encoding.
------------------------------------------------
 State                              | Encoding
------------------------------------------------
 reset                              | 0000
 deb0                               | 0001
 deb1                               | 0010
 modulepresent                      | 0011
 nomodule                           | 0100
 modknownidsel1func1                | 0101
 modknownidsel1func0                | 0110
 modknownidsel0func0                | 0111
 modknownidsel0func1                | 1000
 drvidsellow                        | 1001
 eneerdlines                        | 1010
 eemode                             | 1011
 exiteemode                         | 1100
 exiteewaitidsel                    | 1101
 waitaftereetocheckformoduleremoval | 1110
------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/FSM_40> on signal <cState[1:3]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 idle            | 000
 sendreadcommand | 001
 sendaddrmsb     | 010
 sendaddrlsb     | 011
 getdata         | 100
 setdonesignal   | 101
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModuleIdSm/FSM_53> on signal <cState[1:4]> with user encoding.
---------------------------------
 State               | Encoding
---------------------------------
 nomodulepresent     | 0000
 idle                | 0001
 settoeemode         | 0010
 waitforeeread       | 0011
 correctdatareceived | 0100
 waitformsnoterror   | 0101
 waitformserror      | 0110
 moduleerror         | 0111
 nextmsnoterror      | 1000
 nexteemode          | 1001
 nextmserror         | 1010
---------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/SpiEngine/FSM_54> on signal <cState[1:4]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 idle              | 0000
 waitforcs         | 0001
 waitforspiclkhigh | 0010
 waitforspiclklow  | 0011
 holdcs            | 0100
 setdonereleasecs  | 0101
 setdoneholdcs     | 0110
 releasecs         | 0111
 waitforcshigh     | 1000
 waitandrun        | 1001
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/FSM_42> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/FSM_42> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/FSM_42> on signal <cState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 seteerun           | 001
 waitforeedone      | 010
 setenablechaindone | 011
 nexteerun          | 100
 nextsetdone        | 101
 nextidle           | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/Crio9211IoHandlerx/FSM_62> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/Crio9211IoHandlerx/FSM_62> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/Crio9211IoHandlerx/FSM_62> on signal <cState[1:4]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 idle            | 0000
 findchannel     | 0001
 firstreset      | 0010
 sendchan        | 0011
 sendrdatac      | 0100
 convpulsewait   | 0101
 sendconvpulse   | 0110
 waitfordatadone | 0111
 readdata        | 1000
 secondreset     | 1001
 nextchannel     | 1010
 nextidle        | 1011
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/Crio9211IoHandlerx/FSM_63> on signal <cSpiState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/Crio9211IoHandlerx/FSM_63> on signal <cSpiState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/Crio9211IoHandlerx/FSM_63> on signal <cSpiState[1:2]> with user encoding.
--------------------------
 State        | Encoding
--------------------------
 sendlastbyte | 00
 sendbyte     | 01
 waitforrun   | 10
--------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/Crio9211EnableChainHandlerx/FSM_59> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/Crio9211EnableChainHandlerx/FSM_59> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/Crio9211EnableChainHandlerx/FSM_59> on signal <cState[1:4]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 waitforid         | 0000
 idle              | 0001
 eepromnoerror     | 0010
 incorrectmodule   | 0011
 eepromthencheckid | 0100
 nextidlenoerror   | 0101
 nextwaitforid     | 0110
 nextwaitforid2    | 0111
 waitfordatadone   | 1000
 initmodule        | 1001
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/FSM_38> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/FSM_38> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/FSM_38> on signal <cState[1:4]> with user encoding.
------------------------------------------------
 State                              | Encoding
------------------------------------------------
 reset                              | 0000
 deb0                               | 0001
 deb1                               | 0010
 modulepresent                      | 0011
 nomodule                           | 0100
 modknownidsel1func1                | 0101
 modknownidsel1func0                | 0110
 modknownidsel0func0                | 0111
 modknownidsel0func1                | 1000
 drvidsellow                        | 1001
 eneerdlines                        | 1010
 eemode                             | 1011
 exiteemode                         | 1100
 exiteewaitidsel                    | 1101
 waitaftereetocheckformoduleremoval | 1110
------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/FSM_40> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/FSM_40> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/FSM_40> on signal <cState[1:3]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 idle            | 000
 sendreadcommand | 001
 sendaddrmsb     | 010
 sendaddrlsb     | 011
 getdata         | 100
 setdonesignal   | 101
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModuleIdSm/FSM_60> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModuleIdSm/FSM_60> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModuleIdSm/FSM_60> on signal <cState[1:4]> with user encoding.
---------------------------------
 State               | Encoding
---------------------------------
 nomodulepresent     | 0000
 idle                | 0001
 settoeemode         | 0010
 waitforeeread       | 0011
 correctdatareceived | 0100
 waitformsnoterror   | 0101
 waitformserror      | 0110
 moduleerror         | 0111
 nextmsnoterror      | 1000
 nexteemode          | 1001
 nextmserror         | 1010
---------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/SpiEngine/FSM_61> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/SpiEngine/FSM_61> on signal <cState[1:4]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/SpiEngine/FSM_61> on signal <cState[1:4]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 idle              | 0000
 waitforcs         | 0001
 waitforspiclkhigh | 0010
 waitforspiclklow  | 0011
 holdcs            | 0100
 setdonereleasecs  | 0101
 setdoneholdcs     | 0110
 releasecs         | 0111
 waitforcshigh     | 1000
 waitandrun        | 1001
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRio9211GetCalConst/FSM_64> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRio9211GetCalConst/FSM_64> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRio9211GetCalConst/FSM_64> on signal <cState[1:3]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 waittorun       | 000
 idle            | 001
 waitforcalconst | 010
 getnextcalconst | 011
 checkcrcresult  | 100
 savedata        | 101
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRio9211CalData/FSM_65> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRio9211CalData/FSM_65> on signal <cState[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRio9211CalData/FSM_65> on signal <cState[1:2]> with user encoding.
-------------------------
 State       | Encoding
-------------------------
 idle        | 00
 latchmult00 | 01
 latchmult01 | 10
 donemult    | 11
-------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/FSM_42> on signal <cState[1:3]> with user encoding.
--------------------------------
 State              | Encoding
--------------------------------
 idle               | 000
 seteerun           | 001
 waitforeedone      | 010
 setenablechaindone | 011
 nexteerun          | 100
 nextsetdone        | 101
 nextidle           | 110
--------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/Gen9213ModuleSpecific.Crio9213IoHandler/FSM_69> on signal <cState[1:5]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 idle              | 00000
 idlenotready      | 00001
 waitfordone       | 00010
 spistarted        | 00011
 getdata           | 00100
 nextconfigmode    | 00101
 setconfigrun      | 00110
 sendconfig        | 00111
 waitconfigdone    | 01000
 nextconfigdone    | 01001
 setconfigdone     | 01010
 loadfirstchan     | 01011
 sendchan          | 01100
 convert           | 01101
 readbackconfig    | 01110
 waitconfigmode    | 01111
 waitreconfigdelay | 10000
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/FSM_38> on signal <cState[1:4]> with user encoding.
------------------------------------------------
 State                              | Encoding
------------------------------------------------
 reset                              | 0000
 deb0                               | 0001
 deb1                               | 0010
 modulepresent                      | 0011
 nomodule                           | 0100
 modknownidsel1func1                | 0101
 modknownidsel1func0                | 0110
 modknownidsel0func0                | 0111
 modknownidsel0func1                | 1000
 drvidsellow                        | 1001
 eneerdlines                        | 1010
 eemode                             | 1011
 exiteemode                         | 1100
 exiteewaitidsel                    | 1101
 waitaftereetocheckformoduleremoval | 1110
------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/FSM_40> on signal <cState[1:3]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 idle            | 000
 sendreadcommand | 001
 sendaddrmsb     | 010
 sendaddrlsb     | 011
 getdata         | 100
 setdonesignal   | 101
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModuleIdSm/FSM_66> on signal <cState[1:4]> with user encoding.
---------------------------------
 State               | Encoding
---------------------------------
 nomodulepresent     | 0000
 idle                | 0001
 settoeemode         | 0010
 waitforeeread       | 0011
 correctdatareceived | 0100
 waitformsnoterror   | 0101
 waitformserror      | 0110
 moduleerror         | 0111
 nextmsnoterror      | 1000
 nexteemode          | 1001
 nextmserror         | 1010
---------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/SpiEngine/FSM_67> on signal <cState[1:4]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 idle              | 0000
 waitforcs         | 0001
 waitforspiclkhigh | 0010
 waitforspiclklow  | 0011
 holdcs            | 0100
 setdonereleasecs  | 0101
 setdoneholdcs     | 0110
 releasecs         | 0111
 waitforcshigh     | 1000
 waitandrun        | 1001
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/Crio9213EnableChainHandler/FSM_68> on signal <cState[1:4]> with user encoding.
-------------------------------
 State             | Encoding
-------------------------------
 waitforid         | 0000
 incorrectmodule   | 0001
 waitforeepromdone | 0010
 idle              | 0011
 eeprom            | 0100
 iorequested       | 0101
 nextidlenoerror   | 0110
 nextwaitforid     | 0111
 reid              | 1000
 waittoruneeprom   | 1001
-------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/Gen9213ModuleSpecific.Crio9213GetCalConstx/FSM_70> on signal <cState[1:3]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 waittorun       | 000
 idle            | 001
 waitforcalconst | 010
 getnextcalconst | 011
 checkcrcresult  | 100
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/Crio9213FxpScaleDatax/FSM_71> on signal <cState[1:3]> with user encoding.
-------------------------
 State       | Encoding
-------------------------
 idle        | 000
 latchmult00 | 001
 latchmult01 | 010
 latchmult10 | unreached
 latchmult11 | unreached
 donemult    | 101
-------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/Crio9213UpdateHandler/FSM_72> on signal <cState[1:2]> with user encoding.
--------------------------
 State        | Encoding
--------------------------
 idle         | 00
 waittoupdate | 01
 update       | 10
--------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205IoHandlerx/FSM_76> on signal <cState[1:4]> with user encoding.
-------------------------------------
 State                   | Encoding
-------------------------------------
 idle                    | 0000
 findfirsttwochs         | 0001
 genscanline             | 0010
 decideifprimed          | 0011
 notprimedfindnextch     | 0100
 notprimedwaitforscan    | 0101
 notprimedprepforfinish  | 0110
 primedfindnextch        | 0111
 primedwaitforscan       | 1000
 primedprepforfinish     | 1001
 postopfinishfirstch     | 1010
 postopfinishfirstchwait | 1011
 postopfinishsecondch    | 1100
 done                    | 1101
-------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205SetTriggersx/FSM_75> on signal <cSetTriggersState[1:4]> with user encoding.
---------------------------
 State         | Encoding
---------------------------
 idle          | 0000
 setaimodeinit | 0001
 setaipwmhigh  | 0010
 setaipwmlow   | 0011
 setmodeonly   | 0100
 waitaipwm1    | 0101
 waitaipwm2    | 0110
 resetaipwm1   | 0111
 finish        | 1000
---------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/FSM_74> on signal <cState[1:24]> with one-hot encoding.
------------------------------------------------------
 State                    | Encoding
------------------------------------------------------
 powerup                  | 000000000000000000000010
 reset                    | 000000000000000000000001
 checkidsel0              | 000000000000000000000100
 checkidsel1              | 000000000000000000001000
 enableeeprom             | 000000000000000000100000
 checkeeprom              | 000000000000000001000000
 waitfortristate          | 000000000000000100000000
 waitforidsel             | 000000000000001000000000
 idle                     | 000000000000100000000000
 startproperty            | 000000000010000000000000
 waitproperty             | 000000100000000000000000
 waitfortristateafterprop | 000001000000000000000000
 moduleerrorrun           | 000000000000010000000000
 moduleerrordone          | 000100000000000000000000
 waitforpropidsel         | 000010000000000000000000
 nomodule                 | 000000000000000000010000
 updateterminalmode       | 000000001000000000000000
 updateinputrange         | 000000000100000000000000
 enablegetcalconst        | 000000000000000010000000
 runport                  | 000000010000000000000000
 finishport               | 001000000000000000000000
 initoutputs              | 000000000001000000000000
 getcalconst              | 010000000000000000000000
 getcaldone               | 100000000000000000000000
------------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205CommSmx/FSM_73> on signal <cState[1:4]> with user encoding.
------------------------------
 State            | Encoding
------------------------------
 idle             | 0000
 waitafteridsel   | 0001
 waitforcs        | 0010
 eeclkhigh        | 0011
 eeclklow         | 0100
 ioclkhigh        | 0101
 ioclklow         | 0110
 eewrenclkhigh    | 0111
 eewrenclklow     | 1000
 eewrenreleasecs  | 1001
 waitforeewrite   | 1010
 waitforreleasecs | 1011
 releasecs        | 1100
 sendconvert      | 1101
 waitafterconvert | 1110
------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205GetCalConstx/FSM_77> on signal <cState[1:4]> with user encoding.
------------------------------
 State            | Encoding
------------------------------
 waitforrun       | 0000
 savecalconst     | 0001
 waitforcalconst  | 0010
 latchmult00      | 0011
 latchmult01      | 0100
 latchmult10      | 0101
 latchmult11      | 0110
 donemult         | 0111
 waitforfirstmult | 1000
 checkcrcresult   | 1001
------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205CalDatax/FSM_78> on signal <cState[1:2]> with user encoding.
-------------------------
 State       | Encoding
-------------------------
 idle        | 00
 latchmult00 | 01
 latchmult01 | 10
 donemult    | 11
-------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000000_WhileLoop_Diagram/n_SubVI_subMinArray_vi_5980/n_forloop/FSM_1> on signal <state[1:3]> with gray encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000000_WhileLoop_Diagram/n_SubVI_subMaxArray_vi_5937/n_forloop/FSM_1> on signal <state[1:3]> with gray encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_000000de_WhileLoop_Diagram/n_NiFpgaAG_000000e1_SequenceFrame_Diagram/n_forloop/FSM_1> on signal <state[1:3]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 idle_st | 000
 init_st | 001
 run_st  | 011
 loop_st | 110
 end_st  | 010
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_whileloop/FSM_2> on signal <state[1:2]> with user encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_whileloop/FSM_2> on signal <state[1:2]> with user encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_whileloop_2/FSM_2> on signal <state[1:2]> with user encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_whileloop_3/FSM_2> on signal <state[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle_st | 00
 calc_st | 01
 test_st | 10
 end_st  | 11
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_0000008e_WhileLoop_Diagram/n_NiFpgaAG_00000091_SequenceFrame_Diagram/n_forloop/FSM_4> on signal <state[1:3]> with gray encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_0000008e_WhileLoop_Diagram/n_NiFpgaAG_00000091_SequenceFrame_Diagram/n_forloop_2/FSM_4> on signal <state[1:3]> with gray encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_0000008e_WhileLoop_Diagram/n_NiFpgaAG_00000091_SequenceFrame_Diagram/n_forloop_3/FSM_4> on signal <state[1:3]> with gray encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_0000008e_WhileLoop_Diagram/n_NiFpgaAG_00000091_SequenceFrame_Diagram/n_forloop_5/FSM_4> on signal <state[1:3]> with gray encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_0000008e_WhileLoop_Diagram/n_NiFpgaAG_00000091_SequenceFrame_Diagram/n_forloop_6/FSM_4> on signal <state[1:3]> with gray encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_0000008e_WhileLoop_Diagram/n_NiFpgaAG_00000091_SequenceFrame_Diagram/n_forloop_7/FSM_4> on signal <state[1:3]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 idle_st | 000
 init_st | 001
 run_st  | 011
 loop_st | 110
 end_st  | 010
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_0000008e_WhileLoop_Diagram/n_NiFpgaAG_00000091_SequenceFrame_Diagram/n_forloop_4/FSM_5> on signal <state[1:3]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 idle_st | 000
 init_st | 001
 run_st  | 011
 loop_st | 110
 end_st  | 010
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_0000008e_WhileLoop_Diagram/n_NiFpgaAG_00000091_SequenceFrame_Diagram/n_forloop_8/FSM_6> on signal <state[1:3]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 idle_st | 000
 init_st | 001
 run_st  | 011
 loop_st | 110
 end_st  | 010
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_NiFpgaAG_00000058_SequenceFrame_Diagram/n_NiFpgaAG_00000059_WhileLoop_Diagram/n_NiFpgaAG_0000005c_SequenceFrame_Diagram/n_forloop/FSM_3> on signal <state[1:3]> with gray encoding.
---------------------
 State   | Encoding
---------------------
 idle_st | 000
 init_st | 001
 run_st  | 011
 loop_st | 110
 end_st  | 010
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9220SyncResource111/Crio9220SyncResourceLogicx/FSM_7> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9220SyncResource101/Crio9220SyncResourceLogicx/FSM_7> on signal <cState[1:3]> with user encoding.
---------------------------------------
 State                     | Encoding
---------------------------------------
 waitforresholderenablein  | 000
 waitforenableout          | 001
 waitfordatavalid          | 010
 assertenableout           | 011
 waitforresholderenableclr | 100
---------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264SyncResource102/FSM_8> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9264SyncResource103/FSM_8> on signal <cState[1:3]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 idle            | 000
 waitforrequest  | 001
 selectchannel   | 010
 waitforresource | 011
 pulseupdate     | 100
 waitforenclear  | 101
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264SyncResource102/FSM_9> on signal <clkToResRequest[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9264SyncResource103/FSM_9> on signal <clkToResRequest[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213SyncResource109/FSM_10> on signal <cState[1:4]> with one-hot encoding.
----------------------------
 State          | Encoding
----------------------------
 idle           | 0001
 waitforrequest | 0010
 readdata       | 0100
 waitforenclear | 1000
----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9213SyncResource109/FSM_11> on signal <clkToResRequest[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264SyncResource113/FSM_23> on signal <cState[1:3]> with user encoding.
Optimizing FSM <window/theVI/Crio9264SyncResource115/FSM_23> on signal <cState[1:3]> with user encoding.
-----------------------------
 State           | Encoding
-----------------------------
 idle            | 000
 waitforrequest  | 001
 selectchannel   | 010
 waitforresource | 011
 pulseupdate     | 100
 waitforenclear  | 101
-----------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/Crio9264SyncResource113/FSM_24> on signal <clkToResRequest[1:2]> with user encoding.
Optimizing FSM <window/theVI/Crio9264SyncResource115/FSM_24> on signal <clkToResRequest[1:2]> with user encoding.
-------------------
 State | Encoding
-------------------
 00    | 00
 01    | 01
 10    | 10
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/ViControlx/FSM_49> on signal <EnableInBlk.rEnableInState[1:2]> with gray encoding.
------------------------------------------------
 State                              | Encoding
------------------------------------------------
 idle                               | 00
 enableindeasserted                 | 01
 waituntilinternalclocksbecomevalid | unreached
 waituntilcomponentsinit            | 11
 enableinasserted                   | 10
 enableindeassertionnotsupportederr | unreached
------------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/FSM_50> on signal <ClockDomainCrossing.bPushEnState[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 assert1 | 01
 assert2 | 10
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_arb_rw_4/FSM_79> on signal <cState[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 d_transfer | 01
 clrreg     | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_arb_rw_4/FSM_80> on signal <cToResource[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 100   | 100
 001   | 001
 101   | 101
 010   | 010
 110   | 110
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_arb_rw_5/FSM_82> on signal <cState[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 d_transfer | 01
 clrreg     | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_arb_rw_5/FSM_81> on signal <cToResource[1:3]> with user encoding.
-------------------
 State | Encoding
-------------------
 000   | 000
 100   | 100
 001   | 001
 101   | 101
 010   | 010
 110   | 110
-------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_arb_rw_19/FSM_83> on signal <cState[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 d_transfer | 01
 clrreg     | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_arb_rw_24/FSM_84> on signal <cState[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 d_transfer | 01
 clrreg     | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/n_arb_rw_28/FSM_85> on signal <cState[1:2]> with user encoding.
------------------------
 State      | Encoding
------------------------
 idle       | 00
 d_transfer | 01
 clrreg     | 10
------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/DiagramResetx/FSM_51> on signal <DiagramResetFSM.rDiagramResetState[1:3]> with gray encoding.
-----------------------------------------------
 State                             | Encoding
-----------------------------------------------
 idle                              | 000
 waitforexternalcircuittoinit      | 001
 waitforbaseclkstobecomevalid      | 011
 waitforclkenablerequest           | unreached
 waitforgatedbaseclkstobecomevalid | 010
 waitfordervclkstobecomevalid      | 110
 waitforresetassertionduration     | 111
 waitfordiagrstdeasrtpropdly       | 101
 waitforhosttoassertdiagrst        | 100
 diagrstassertionnotsupportederr   | unreached
-----------------------------------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/FSM_52> on signal <ClockDomainCrossing.bPushEnState[1:2]> with user encoding.
---------------------
 State   | Encoding
---------------------
 idle    | 00
 assert1 | 01
 assert2 | 10
---------------------
Analyzing FSM <MFsm> for best encoding.
Optimizing FSM <window/NiFpgaStockDcmInst0/NiFpgaClockManagerControlx/FSM_0> on signal <rCmState[1:2]> with gray encoding.
----------------------------------------------
 State                            | Encoding
----------------------------------------------
 waitforclkintobecomevalid        | 00
 waitforcmtoinitialize            | 01
 waitforcmtolock                  | 11
 waitforbufgenassertionduration   | unreached
 cmrunning                        | 10
 waitforbufgendeassertionduration | unreached
----------------------------------------------
WARNING:Xst:1426 - The value init of the FF/Latch cModuleReqMode_1 hinder the constant cleaning in the block cRio9403LdHandler.
   You should achieve better results by setting this init to 1.
INFO:Xst:1901 - Instance NiFpgaStockDcmInst0/DCMx in unit TheWindow of type DCM has been replaced by DCM_ADV
WARNING:Xst:2973 - All outputs of instance <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/NiFpgaFifoCountControlx> of block <NiFpgaFifoCountControl_3> are unconnected in block <toplevel_gen>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/NiFpgaFifoCountControlx> of block <NiFpgaFifoCountControl_2> are unconnected in block <toplevel_gen>. Underlying logic will be removed.
WARNING:Xst:2973 - All outputs of instance <window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/NiFpgaFifoCountControlx> of block <NiFpgaFifoCountControl_1> are unconnected in block <toplevel_gen>. Underlying logic will be removed.

Optimizing unit <DFlopUnsigned_1> ...

Optimizing unit <DFlop_1> ...

Optimizing unit <DFlopGray_1> ...

Optimizing unit <DoubleSyncBase> ...

Optimizing unit <DoubleSyncAsyncInBase> ...

Optimizing unit <DFlopUnsigned_2> ...

Optimizing unit <DFlopGray_2> ...

Optimizing unit <NiFpgaDualPortRAM_Inferred_3> ...

Optimizing unit <DFlopUnsigned_3> ...

Optimizing unit <DFlopGray_3> ...

Optimizing unit <DFlopSlvResetVal_2> ...

Optimizing unit <CrioCiInputFlops> ...

Optimizing unit <CrioCiOutputMuxes> ...

Optimizing unit <CcMuxSL2> ...

Optimizing unit <arraycollect_232> ...

Optimizing unit <arraycollect_175> ...

Optimizing unit <arraycollect_187> ...

Optimizing unit <DFlopSlvResetVal_1> ...

Optimizing unit <toplevel_gen> ...

Optimizing unit <RegisterAccess> ...

Optimizing unit <RegisterAccess32> ...

Optimizing unit <MiteDmaInput_1> ...

Optimizing unit <DmaMiteReadRegs_1> ...

Optimizing unit <NiFpgaFifoFlags_1> ...

Optimizing unit <SyncFifoFlags_1> ...

Optimizing unit <HandshakeBase> ...

Optimizing unit <DmaDisabler> ...

Optimizing unit <CpuDataRd> ...

Optimizing unit <MiteDmaComponentEnableChain_1> ...

Optimizing unit <NiFpgaFifoPortReset_1> ...

Optimizing unit <MiteDmaInput_2> ...

Optimizing unit <DmaMiteReadRegs_2> ...

Optimizing unit <NiFpgaFifoFlags_2> ...

Optimizing unit <SyncFifoFlags_2> ...

Optimizing unit <MiteDmaComponentEnableChain_2> ...

Optimizing unit <MiteDmaOutput> ...

Optimizing unit <DmaMiteWriteRegs> ...

Optimizing unit <SyncFifoFlags_3> ...

Optimizing unit <CpuDataWr> ...

Optimizing unit <NiFpgaFlipFlopFifo> ...

Optimizing unit <MiteDmaComponentEnableChain_3> ...

Optimizing unit <NiFpgaFifoClearControl_2> ...

Optimizing unit <NiFpgaFifoPortReset_2> ...

Optimizing unit <MiteIrq> ...

Optimizing unit <HandshakeBaseResetCross_2> ...

Optimizing unit <HandshakeBaseResetCross_3> ...

Optimizing unit <Crio9220> ...

Optimizing unit <Crio9223EnableChainHandler> ...

Optimizing unit <EnableChainSM> ...

Optimizing unit <Crio9223IoHandler> ...

Optimizing unit <Crio9223ErrorDecode> ...

Optimizing unit <Crio9220SampleCounter> ...

Optimizing unit <Crio9223SampleValidDelay> ...

Optimizing unit <Crio9223ClockCrossing> ...

Optimizing unit <Crio9220GetCalConst> ...

Optimizing unit <Crio9220CalData> ...

Optimizing unit <Crio9223SampleSerializer> ...

Optimizing unit <CrioCommInt> ...

Optimizing unit <CrioCiCartridgeDetection> ...

Optimizing unit <CrioCiModeSelectorControl> ...

Optimizing unit <CrioCiPinConfig> ...

Optimizing unit <CrioCiSpiEngine> ...

Optimizing unit <CcSpiLogic> ...

Optimizing unit <CcSourceSynchFalling> ...

Optimizing unit <CrioCiEeprom> ...

Optimizing unit <CrioCiCartridgeIdentification> ...

Optimizing unit <CrioCiInitSequence> ...

Optimizing unit <CrioParallelCrcCore> ...

Optimizing unit <CcHsInput> ...

Optimizing unit <CcHsInputLogic> ...

Optimizing unit <cRio9264> ...

Optimizing unit <cRio9264CalData> ...

Optimizing unit <cRio9264IoHandler> ...

Optimizing unit <cRioStock_1> ...

Optimizing unit <cRioStockModuleId_1> ...

Optimizing unit <cRioStockSpiEngine_1> ...

Optimizing unit <cRio9264EnableChainHandler> ...

Optimizing unit <cRio9264UpdateHandler> ...

Optimizing unit <cRio9264GetCalConst> ...

Optimizing unit <cRio9264CalReciprocal> ...

Optimizing unit <cRio9403> ...

Optimizing unit <cRio9403DioHandler> ...

Optimizing unit <cRio9403LdHandler> ...

Optimizing unit <CrioEepromRead_2> ...

Optimizing unit <cRio9403SpiWord> ...

Optimizing unit <cRioStock_2> ...

Optimizing unit <cRioStockModuleId_2> ...

Optimizing unit <cRioStockSpiEngine_2> ...

Optimizing unit <cRio9403EnableChainHandler> ...

Optimizing unit <Crio9211> ...

Optimizing unit <Crio9211IoHandler> ...

Optimizing unit <Crio9211EnableChainHandler> ...

Optimizing unit <cRioStock_3> ...

Optimizing unit <cRioStockModuleId_3> ...

Optimizing unit <cRioStockSpiEngine_3> ...

Optimizing unit <Crio9211GetCalConst> ...

Optimizing unit <cRio9211CalData> ...

Optimizing unit <Crio9213> ...

Optimizing unit <cRio9213IoHandler> ...

Optimizing unit <cRioStock_4> ...

Optimizing unit <cRioStockModuleId_4> ...

Optimizing unit <cRioStockSpiEngine_4> ...

Optimizing unit <Crio9213EnableChainHandler> ...

Optimizing unit <Crio9213GetCalConst> ...

Optimizing unit <Crio9213FxpScaleData> ...

Optimizing unit <cRio9213UpdateHandler> ...

Optimizing unit <cRio9205> ...

Optimizing unit <cRio9205IoHandler> ...

Optimizing unit <cRio9205SetTriggers> ...

Optimizing unit <cRio9205ControlSm> ...

Optimizing unit <cRio9205CommSm> ...

Optimizing unit <CrioSourceSync> ...

Optimizing unit <cRio9205GetCalConst> ...

Optimizing unit <cRio9205CalData> ...

Optimizing unit <NiFpgaAG_00000000_WhileLoop> ...

Optimizing unit <NiLvFxpEnableHandlerSlv_1> ...

Optimizing unit <NiFpgaAG_00000020_ForLoop> ...

Optimizing unit <ArrayIndexNode_27> ...

Optimizing unit <forloop_1> ...

Optimizing unit <NiFpgaAG_00000012_ForLoop> ...

Optimizing unit <NiFpgaLocalResHolderRead_1> ...

Optimizing unit <whileloop> ...

Optimizing unit <NiFpgaAG_00000042_SequenceFrame> ...

Optimizing unit <Crio9403DoIoNode> ...

Optimizing unit <NiFpgaAG_0000004b_SequenceFrame> ...

Optimizing unit <NiFpgaAG_00000058_SequenceFrame> ...

Optimizing unit <NiFpgaAG_000000e1_SequenceFrame> ...

Optimizing unit <NiFpgaAG_000000e2_ForLoop> ...

Optimizing unit <NiFpgaShiftReg_2> ...

Optimizing unit <NiFpgaAG_000000e9_SequenceFrame> ...

Optimizing unit <Crio9403DiIoNode> ...

Optimizing unit <NiFpgaAG_00000091_SequenceFrame> ...

Optimizing unit <NiFpgaMergeErrors_5> ...

Optimizing unit <NiFpgaAG_000000c8_ForLoop> ...

Optimizing unit <arrayLpIndx_202> ...

Optimizing unit <NiLvFxpEnableHandlerSlv_4> ...

Optimizing unit <NiLvFixedToFloat_1> ...

Optimizing unit <FxpNormalize_1> ...

Optimizing unit <forloop_3> ...

Optimizing unit <arrayLpIndx_185> ...

Optimizing unit <NiLvFixedToFloat_2> ...

Optimizing unit <FxpNormalize_2> ...

Optimizing unit <forloop_4> ...

Optimizing unit <forloop_5> ...

Optimizing unit <NiFpgaAG_0000005d_SequenceFrame> ...

Optimizing unit <NiFpgaMergeErrors_4> ...

Optimizing unit <NiFpgaAG_00000082_ForLoop> ...

Optimizing unit <arrayLpIndx_132> ...

Optimizing unit <forloop_2> ...

Optimizing unit <NiFpgaAG_000000fb_SequenceFrame> ...

Optimizing unit <NiFpgaMergeErrors_7> ...

Optimizing unit <Crio9220SyncResourceLogic> ...

Optimizing unit <Crio9264SyncResource_1> ...

Optimizing unit <bushold> ...

Optimizing unit <HandshakeBaseResetCross_1> ...

Optimizing unit <NiFpgaRegFrameworkShiftReg_2> ...

Optimizing unit <NiFpgaRegFrameworkShiftReg_1> ...

Optimizing unit <Crio9403SyncResource_1> ...

Optimizing unit <Crio9403SyncResource_2> ...

Optimizing unit <Crio9211SyncResource_1> ...

Optimizing unit <Crio9211SyncResource_2> ...

Optimizing unit <Crio9213SyncResource> ...

Optimizing unit <cRio9205_SyncRes> ...

Optimizing unit <Crio9403SyncResource_3> ...

Optimizing unit <Crio9264SyncResource_2> ...

Optimizing unit <Crio9403SyncResource_4> ...

Optimizing unit <ViControl> ...

Optimizing unit <SafeBusCrossing_1> ...

Optimizing unit <HandshakeBaseResetCross_4> ...

Optimizing unit <NiFpgaHostAccessibleRegister_3> ...

Optimizing unit <NiFpgaHostAccessibleRegister_5> ...

Optimizing unit <NiFpgaHostAccessibleRegister_6> ...

Optimizing unit <NiFpgaHostAccessibleRegister_7> ...

Optimizing unit <NiFpgaHostAccessibleRegister_8> ...

Optimizing unit <IDSel_Timer> ...

Optimizing unit <NiFpgaArbRW_3> ...

Optimizing unit <NiFpgaArbPowerOf2_1> ...

Optimizing unit <NiFpgaArbRW_4> ...

Optimizing unit <NiFpgaArbSerializeAccess_2> ...

Optimizing unit <NiFpgaArbPowerOf2_2> ...

Optimizing unit <NiFpgaArbRW_11> ...

Optimizing unit <NiFpgaArbRW_15> ...

Optimizing unit <NiFpgaArbPowerOf2_3> ...

Optimizing unit <NiFpgaArbRW_18> ...

Optimizing unit <DiagramReset> ...

Optimizing unit <SafeBusCrossing_2> ...

Optimizing unit <HandshakeBaseResetCross_5> ...

Optimizing unit <NiFpgaClockManagerControl> ...
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/Crio9223ClockCrossingx, both signals cSleep and window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqNum/iPush have a KEEP attribute, signal cSleep will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Trig.TrigMux/aSel and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Trig.TrigMux/aSel will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Done_n.Done_nMux/aSel and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Done_n.Done_nMux/aSel will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Func.FuncMux/aSel and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Func.FuncMux/aSel will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Miso.MisoMux/aSel and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Miso.MisoMux/aSel will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Mosi.MosiMux/aSel and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/Cs_n.Cs_nMux/aSel have a KEEP attribute, signal Mosi.MosiMux/aSel will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals OClk.OClkMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal OClk.OClkMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Trig.TrigMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Trig.TrigMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Done_n.Done_nMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Done_n.Done_nMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Conv_n.Conv_nMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Conv_n.Conv_nMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Cs_n.Cs_nMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Cs_n.Cs_nMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Miso.MisoMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Miso.MisoMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> will be lost.
WARNING:Xst:1303 - From in and out of unit window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx, both signals Mosi.MosiMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> and window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel have a KEEP attribute, signal Mosi.MosiMux/Mux4.MuxLoop[1].MuxLocalSpace.Mux2Decide.MuxDecidedSpace.aDataInLocal<0> will be lost.
WARNING:Xst:638 - in unit toplevel_gen Conflict on KEEP property on signal N1 and window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/BlkOut.oDataAckClkEnable window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/BlkOut.oDataAckClkEnable signal will be lost.
WARNING:Xst:638 - in unit toplevel_gen Conflict on KEEP property on signal N1 and window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.oDataAckClkEnable window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.oDataAckClkEnable signal will be lost.
WARNING:Xst:638 - in unit toplevel_gen Conflict on KEEP property on signal window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel and window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cState_FSM_FFd11 window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cState_FSM_FFd11 signal will be lost.
WARNING:Xst:638 - in unit toplevel_gen Conflict on KEEP property on signal window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel and window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cState_FSM_FFd6 window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cState_FSM_FFd6 signal will be lost.
WARNING:Xst:638 - in unit toplevel_gen Conflict on KEEP property on signal window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel and window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cState_FSM_FFd5 window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cState_FSM_FFd5 signal will be lost.

Mapping all equations...
WARNING:Xst - Unrecognized value ibuf. Accepted values for attribute buffer_type on local signal <dio46> are: BUFG, BUFR, BUFH or NONE. Constraint is ignored.
WARNING:Xst:1287 - Bad buffer "ibuf" constraint for inout port <dio46>
Building and optimizing final netlist ...
Changing polarity of register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cIdSelEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cOthersEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cOthersEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cOthersEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cOthersEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cOthersEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cEeOutputsEn_3 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cIdSelEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cOthersEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_3 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cIdSelEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cOthersEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cEeOutputsEn_3 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_9 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_9 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_5 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_5 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_7 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_7 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_7_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_7_1 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_3 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_3 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_8 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_8 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdSelEn to handle IOB=TRUE attribute
Replicating register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdOutputsEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdOutputsEn to handle IOB=TRUE attribute
Replicating register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdOutputsEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdOutputsEn_1 to handle IOB=TRUE attribute
Replicating register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cConvEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdOutputsEn_3 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cIdSelEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cOthersEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cOthersEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cEeOutputsEn_3 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cOthersEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cIdSelEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cOthersEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_3 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cIdSelEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_1 to handle IOB=TRUE attribute
Replicating register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_2 to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cOthersEn to handle IOB=TRUE attribute
Changing polarity of register window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn_3 to handle IOB=TRUE attribute
Found area constraint ratio of 100 (+ 5) on block toplevel_gen, actual ratio is 136.
Optimizing block <toplevel_gen> to meet ratio 100 (+ 5) of 4800 slices :
WARNING:Xst:2254 - Area constraint could not be met for block <toplevel_gen>, final ratio is 136.
Replicating register window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/Crio9213UpdateHandler/cConv_n_out to handle IOB=TRUE attribute

FlipFlop window/theVI/Crio9211Resource2/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn has been replicated 3 time(s)
FlipFlop window/theVI/Crio9211Resource7/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn has been replicated 3 time(s)
FlipFlop window/theVI/Crio9211Resource8/Crio9211ResourceCorex/Crio9211x/cRioStock/ModeSelector/cEeOutputsEn has been replicated 3 time(s)
FlipFlop window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cEeOutputsEn has been replicated 3 time(s)
FlipFlop window/theVI/Crio9213Resource1/Crio9213ResourceCorex/Crio9213x/CrioStock/ModeSelector/cOthersEn has been replicated 2 time(s)
FlipFlop window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_3 has been replicated 1 time(s)
FlipFlop window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_5 has been replicated 1 time(s)
FlipFlop window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_7 has been replicated 2 time(s)
FlipFlop window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_8 has been replicated 1 time(s)
FlipFlop window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiModeSelectorx/CrioCiPinConfigx/cCrioBusOe_9 has been replicated 1 time(s)
FlipFlop window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cEeOutputsEn has been replicated 3 time(s)
FlipFlop window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/ModeSelector/cOthersEn has been replicated 1 time(s)
FlipFlop window/theVI/Crio9403Resource3/Crio9403ResourceCorex/Crio9403x/cRioStock/ModeSelector/cEeOutputsEn has been replicated 3 time(s)
FlipFlop window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205ControlSmx/cIdOutputsEn has been replicated 3 time(s)

Final Macro Processing ...

Processing Unit <toplevel_gen> :
	Found 2-bit shift register for signal <window/mBusReset>.
	Found 2-bit shift register for signal <window/theVI/ViControlx/bEnableOut>.
Unit <toplevel_gen> processed.

=========================================================================
Final Register Report

Macro Statistics
# Registers                                            : 14887
 Flip-Flops                                            : 14887
# Shift Registers                                      : 2
 2-bit shift register                                  : 2

=========================================================================

=========================================================================
*                           Partition Report                            *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Design Summary                             *
=========================================================================

Clock Information:
------------------
----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------+
Clock Signal                                                                                                    | Clock buffer(FF name)                                                                                                           | Load  |
----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------+
Clk40                                                                                                           | DCM_ADV:CLK2X                                                                                                                   | 770   |
Clk40                                                                                                           | IBUFG+BUFG                                                                                                                      | 13773 |
MiteClk                                                                                                         | IBUFG+BUFG                                                                                                                      | 1010  |
window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel| NONE(window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/BlkOut.oPushToggleToReadyx/DFlopx/FDCPEx)| 46    |
dio46                                                                                                           | IBUF                                                                                                                            | 2     |
----------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------------------------------------------------------------------------+-------+
INFO:Xst:2169 - HDL ADVISOR - Some clock signals were not automatically buffered by XST with BUFG/BUFR resources. Please use the buffer_type constraint in order to insert these buffers to the clock signals to help prevent skew problems.

Asynchronous Control Signals Information:
----------------------------------------
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
Control Signal                                                                                                                                                                                                                                                                                                                                                                                   | Buffer(FF name)                                                                                                                                                                                                                                                  | Load  |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+
window/theVI/DiagramResetx/DiagramResetRegisterBlk.aDiagramResetLoc(window/theVI/DiagramResetx/DiagramResetRegisterBlk.AsyncDiagramRst/FDCPEx:Q)                                                                                                                                                                                                                                                 | BUFG(window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/Crio9220Initializerx/Crio9220GetCalConstx/cCalMemWrData_1)                                                                                                                                   | 14253 |
window/theVI/Crio9220Resource4/Crio9220ResourceCorex/Crio9220x/CrioCommIntx/CrioCiOutputMuxesx/OClk.OClkMux/aSel(XST_GND:G)                                                                                                                                                                                                                                                                      | NONE(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.BlkFifo.NiFpgaFifox/NiFpgaFifoFlagsx/BlkAddr.SyncToIClkx/cAddrAUnsignedx/GenFlops[0].DFlopx/FDCPEx)| 833   |
window/aBusReset(window/aBusReset1:O)                                                                                                                                                                                                                                                                                                                                                            | NONE(window/theVI/n_bushold/MiteClkShifter.ShiftRegister/SyncBusReset/PulseSyncBasex/iHoldSigInx/FDCPEx)                                                                                                                                                         | 421   |
window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/N0(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/XST_GND:G)| NONE(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/iDlySigx/FDCPEx)                                                  | 3     |
window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/N0(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/XST_GND:G)    | NONE(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/FDCPEx)                                | 3     |
window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/N0(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/XST_GND:G)| NONE(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.FromPushDblSync/DoubleSyncBasex/iDlySigx/FDCPEx)                                                  | 3     |
window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/N0(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/XST_GND:G)    | NONE(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Input.FifoClearController/PushSynchNeeded.ToPushDblSync/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/FDCPEx)                                | 3     |
window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Output.FifoClearController/PopSynchNeeded.FromPopDblSync/DoubleSyncBasex/N0(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Output.FifoClearController/PopSynchNeeded.FromPopDblSync/DoubleSyncBasex/XST_GND:G)  | NONE(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Output.FifoClearController/PopSynchNeeded.FromPopDblSync/DoubleSyncBasex/iDlySigx/FDCPEx)                                                   | 3     |
window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Output.FifoClearController/PopSynchNeeded.ToPopDblSync/DoubleSyncBasex/N0(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Output.FifoClearController/PopSynchNeeded.ToPopDblSync/DoubleSyncBasex/XST_GND:G)      | NONE(window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChannel.MiteDmaComponentx/EnableChains/Output.FifoClearController/PopSynchNeeded.ToPopDblSync/DoubleSyncBasex/DoubleSyncAsyncInBasex/oSigx/FDCPEx)                                 | 3     |
window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/iIResetFast(window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q)                                                                                                             | NONE(window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkIn.iPushTogglex/DFlopx/FDCPEx)                                                                                                                | 1     |
window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/iIResetFast(window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q)                                                                                                                   | NONE(window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCrossing.BusClkToReliableClkHS/BlkIn.iPushTogglex/DFlopx/FDCPEx)                                                                                                                   | 1     |
window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205CommSmx/GenerateSsClkShiftReg.CrioSourceSync/oEdgeDetectedFE(window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205CommSmx/GenerateSsClkShiftReg.CrioSourceSync/oEdgeDetectedFE:Q)                                                                                                                     | NONE(window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205CommSmx/GenerateSsClkShiftReg.CrioSourceSync/aEdgeDetectorOutput)                                                                                                                   | 1     |
window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/iIResetFast(window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q)                                                                                                                                                               | NONE(window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqAck/BlkIn.iPushTogglex/DFlopx/FDCPEx)                                                                                                                                         | 1     |
window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqNum/BlkOut.SyncIReset/c1NxResetFastLcl(window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqNum/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q)                                                                                                                                        | NONE(window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeIrqNum/BlkIn.iPushTogglex/DFlopx/FDCPEx)                                                                                                                                         | 1     |
window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/iIResetFast(window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q)                                                                                                                                                                                                                   | NONE(window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkIn.iPushTogglex/DFlopx/FDCPEx)                                                                                                                                                                   | 1     |
INFO:TclTasksC:1850 - process run : Synthesize - XST is done.
window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/iIResetFast(window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncIReset/c1ResetFastLclx/DFlopx/FDCPEx:Q)                                                                                                                                                                                                                       | NONE(window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkIn.iPushTogglex/DFlopx/FDCPEx)                                                                                                                                                                     | 1     |
-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+-------+

Timing Summary:
---------------
Speed Grade: -1

   Minimum period: 12.906ns (Maximum Frequency: 77.485MHz)
   Minimum input arrival time before clock: 5.423ns
   Maximum output required time after clock: 4.776ns
   Maximum combinational path delay: No path found

=========================================================================
WARNING:Xst:615 - Flip flop associated with net dio10 not found, property IOB not attached.
WARNING:Xst:615 - Flip flop associated with net dio48 not found, property IOB not attached.
WARNING:Xst:615 - Flip flop associated with net dio60 not found, property IOB not attached.
WARNING:Xst:615 - Flip flop associated with net dio70 not found, property IOB not attached.
WARNING:Xst:3152 - You have chosen to run a version of XST which is not the default solution
   for the specified device family. You are free to use it in order to take
   advantage of its enhanced HDL parsing/elaboration capabilities. However,
   please be aware that you may be impacted by  language support differences.
   This version may also result in circuit performance and device utilization
   differences for your particular design. You can always revert back to the
   default XST solution by setting the "use_new_parser" option to value "no" 
   on the XST command line or in the XST process properties panel.

Process "Synthesize - XST" completed successfully
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Adapter16.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_246.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_27.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataRd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataWr.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio80MhzClkRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9205ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9208IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213FxpScaleData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Initializer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SampleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResourceLogic.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ClockCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ErrorDecode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223HseioReadHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoNodeResHolder.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleSerializer.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleValidDelay.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403CommHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DiIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DioHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DoIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403LdHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SpiWord.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeDetection.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeIdentification.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCrcCheck.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiEeprom.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInitSequence.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInputFlops.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelectorControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiOutputMuxes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPicoBeatleInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPinConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPulseMask.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioClockCondition.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioParallelCrcCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioSourceSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForAnsteuerung_beenden_ctl_0RHFpgaRe
   adPortOnResbushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForMiteIoLikePortOnResInterface.vhd"
   into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTmax_ctl_5RHFpgaReadPortOnResbush
   old.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTopEnablesPortOnResTopEnablePassT
   hru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbFordinPortOnResSleep.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolVec.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSlvResetVal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopUnsigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DiagramReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaDisabler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteReadRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteWriteRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncAsyncInBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBoolAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSlAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainSM.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainWithTimeout.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FeedbackNonSctlCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoReadAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoWriteAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FloatingFeedbackGInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpAddSub.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivPreproc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivRnd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivSigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDynamicShift.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpNormalize.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpShiftCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/GenDataValid.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBaseResetCross.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/IDSel_Timer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Interface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/InvisibleResholder.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponent.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponentEnableChain.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaInput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaOutput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterfaceOutputEnables.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteIrq.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteReadInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteWriteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000001_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000012_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000020_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructure_64.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002e_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000032_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000041_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000042_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000004b_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000058_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000059_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005a_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005c_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000082_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008e_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008f_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000091_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000092_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000ac_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000bc_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000de_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000df_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e1_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e2_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e9_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000fb_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000010d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_Speichern4_dash_2FPGA.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbDelayer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbPowerOf2.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbRW.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbSerializeAccess.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOpNot.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaClockManagerControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaCtrlIndRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam_Inferred.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoClearControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoCountControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPopBuffer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPortReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFlipFlopFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaHostAccessibleRegister.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderRead.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderWrite.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLoopTimer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMergeErrors.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteReadInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteWriteInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPipelinedOrGateTreeSlv.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPulseSyncBaseWrapper.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegFrameworkShiftReg.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCoreBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaShiftReg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleModuloCounter.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaStockDcm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFixedToFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompareCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivideCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiplyCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixed.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixedCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandlerSlv.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiCycleEnableHandler.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFixedPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFloatingPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToInteger.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Divide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Equal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Greater.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32GreaterOrEqual.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Less.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32LessOrEqual.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Multiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32NotEqual.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommIntConfiguration.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommunicationInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9211Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9223Shared.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9403IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpArithmetic.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaArbiter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaCoresFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifoGenericValue.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaIrqRegisters.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaViControlRegister.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiLvPrims.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess32.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ResetSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SafeBusCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Sleep.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrInd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrIndOpt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SyncFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TheWindow.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TimeoutManager.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TopEnablePassThru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViSignature.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_132.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_173.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_185.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_189.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_202.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_136.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_175.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_187.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_232.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/bushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CommSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205ControlSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GenScanLine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SetTriggers.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SettingRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_SyncRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_io.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalReciprocal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMemory.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalParallelCrc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStock.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModuleId.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/forloop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_r_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_w_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMaxArray_vi_colon_Clone0.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMinArray_vi.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/whileloop.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -u -uc toplevel_gen.ucf -p xc5vlx30-ff676-1 toplevel_gen.ngc toplevel_gen.ngd

Command Line: C:\NIFPGA\programs\Xilinx13_4\ISE\bin\nt\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -aul -nt timestamp -u -uc toplevel_gen.ucf -p
xc5vlx30-ff676-1 toplevel_gen.ngc toplevel_gen.ngd

Reading NGO file "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.ngc" ...
Loading design module
"C:\NIFPGA\jobs\G2K2D0O_KSw9nkc/NiLvXipFloat32Divide.ngc"...
Loading design module
"C:\NIFPGA\jobs\G2K2D0O_KSw9nkc/NiLvXipFloat32Multiply.ngc"...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "toplevel_gen.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoAddr<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoDmaAck_n<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoRd_n'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoWt_n'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoRamSel_n'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromDataAddrDackIorIowRamsel"= "mIoData<*>"
   "AsyncFromAddrDackIorIowRamsel";> [toplevel_gen.ucf(713)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'mIoData<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromDataAddrDackIorIowRamsel"= "mIoData<*>"
   "AsyncFromAddrDackIorIowRamsel";> [toplevel_gen.ucf(713)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'AsyncFromAddrDackIorIowRamsel'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtk"= "aIoInt*"
   "mIoDmaReq<*>" "mIoDtack_n";> [toplevel_gen.ucf(714)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'aIoInt*'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtk"= "aIoInt*"
   "mIoDmaReq<*>" "mIoDtack_n";> [toplevel_gen.ucf(714)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'mIoDmaReq<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtk"= "aIoInt*"
   "mIoDmaReq<*>" "mIoDtack_n";> [toplevel_gen.ucf(714)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'mIoDtack_n'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtkRdyData"=
   "AsyncToIrqDrqDtk" "mIoReady" "mIoData<*>";> [toplevel_gen.ucf(715)]: Unable
   to find an active 'TNM' or 'TimeGrp' constraint named 'AsyncToIrqDrqDtk'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtkRdyData"=
   "AsyncToIrqDrqDtk" "mIoReady" "mIoData<*>";> [toplevel_gen.ucf(715)]: Unable
   to find an active 'TNM' or 'TimeGrp' constraint named 'mIoReady'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtkRdyData"=
   "AsyncToIrqDrqDtk" "mIoReady" "mIoData<*>";> [toplevel_gen.ucf(715)]: Unable
   to find an active 'TNM' or 'TimeGrp' constraint named 'mIoData<*>'.

ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite0_17"= FROM
   PADS(AsyncFromDataAddrDackIorIowRamsel) TO PADS(AsyncToIrqDrqDtk) 0 ns;>
   [toplevel_gen.ucf(717)]: PADS "AsyncFromDataAddrDackIorIowRamsel" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite0_17"= FROM
   PADS(AsyncFromDataAddrDackIorIowRamsel) TO PADS(AsyncToIrqDrqDtk) 0 ns;>
   [toplevel_gen.ucf(717)]: PADS "AsyncToIrqDrqDtk" not found.  Please verify
   that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite18_22"= FROM
   PADS(AsyncFromAddrDackIorIowRamsel) TO PADS(mIoData<*>) 0 ns;>
   [toplevel_gen.ucf(721)]: PADS "AsyncFromAddrDackIorIowRamsel" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite23_28"= FROM
   PADS(AsyncFromDataAddrDackIorIowRamsel) TO PADS(mIoReady) 0 ns;>
   [toplevel_gen.ucf(724)]: PADS "AsyncFromDataAddrDackIorIowRamsel" not found. 
   Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite29_33"= FROM
   PADS(mIoHWord_n) TO PADS(AsyncToIrqDrqDtkRdyData) 0 ns;>
   [toplevel_gen.ucf(727)]: PADS "mIoHWord_n" not found.  Please verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:59 - Constraint <TIMESPEC "TS_AsynchMite29_33"= FROM
   PADS(mIoHWord_n) TO PADS(AsyncToIrqDrqDtkRdyData) 0 ns;>
   [toplevel_gen.ucf(727)]: PADS "AsyncToIrqDrqDtkRdyData" not found.  Please
   verify that:
   1. The specified design element actually exists in the original design.
   2. The specified object is spelled correctly in the constraint source file.

ERROR:ConstraintSystem:58 - Constraint <INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*iHoldSigInx/FDCPEx" TNM =
   TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx;>
   [toplevel_gen.ucf(734)]: INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*iHoldSigInx/FDCPEx" does not
   match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*oHoldSigIn_msx/FDCPEx" TNM =
   TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx;>
   [toplevel_gen.ucf(735)]: INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*oHoldSigIn_msx/FDCPEx" does
   not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*oSigReturn*" TNM =
   TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx;>
   [toplevel_gen.ucf(736)]: INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*oSigReturn*" does not match
   any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*iSigOut_msx/FDCPEx" TNM =
   TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx;>
   [toplevel_gen.ucf(737)]: INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*iSigOut_msx/FDCPEx" does not
   match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*oLocalSigOutCEx/FDCPEx" TNM =
   TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx;>
   [toplevel_gen.ucf(738)]: INST
   "*Crio9220Resource4/*/PulseSyncIdSelTimerTickx/*oLocalSigOutCEx/FDCPEx" does
   not match any design objects.

ERROR:ConstraintSystem:58 - Constraint <INST
   "*n_bushold/*ShiftRegister/SyncBusReset/*oSigReturn*" TNM =
   TNM_oSigReturn_n_bushold/*ShiftRegister/SyncBusReset;>
   [toplevel_gen.ucf(745)]: INST
   "*n_bushold/*ShiftRegister/SyncBusReset/*oSigReturn*" does not match any
   design objects.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo0"= FROM
   "TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 37.1212503750
   ns DATAPATHONLY;> [toplevel_gen.ucf(772)]: Unable to find an active 'TimeGrp'
   or 'TNM' or 'TPSync' constraint named
   'TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo0"= FROM
   "TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 37.1212503750
   ns DATAPATHONLY;> [toplevel_gen.ucf(772)]: Unable to find an active 'TimeGrp'
   or 'TNM' or 'TPSync' constraint named
   'TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo1"= FROM
   "TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(773)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo1"= FROM
   "TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(773)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo2"= FROM
   "TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(774)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo2"= FROM
   "TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(774)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo22"= FROM
   "TNM_oSigReturn_n_bushold/*ShiftRegister/SyncBusReset" TO
   "TNM_iSigOut_msn_bushold/*ShiftRegister/SyncBusReset" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(794)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_oSigReturn_n_bushold/*ShiftRegister/SyncBusReset'.

ERROR:ConstraintSystem:58 - Constraint <TIMESPEC "TS_CustomFromTo50"= FROM
   FFS(*ViControlx*rGatedClkStartupErr) TO
   FFS(*ViControlx*bGatedClkStartupErr_ms) 181.6141820162 ns DATAPATHONLY;>
   [toplevel_gen.ucf(822)]: FFS "*ViControlx*rGatedClkStartupErr" does not match
   any design objects.

ERROR:ConstraintSystem:58 - Constraint <TIMESPEC "TS_CustomFromTo51"= FROM
   FFS(*ViControlx*rEnableDeassertionErr) TO
   FFS(*ViControlx*bEnableDeassertionErr_ms) 181.6141820162 ns DATAPATHONLY;>
   [toplevel_gen.ucf(823)]: FFS "*ViControlx*rEnableDeassertionErr" does not
   match any design objects.

ERROR:ConstraintSystem:58 - Constraint <TIMESPEC "TS_CustomFromTo52"= FROM
   FFS(*ViControlx*rDiagramResetAssertionErr) TO
   FFS(*ViControlx*bDiagramResetAssertionErr_ms) 181.6141820162 ns
   DATAPATHONLY;> [toplevel_gen.ucf(824)]: FFS
   "*ViControlx*rDiagramResetAssertionErr" does not match any design objects.


WARNING:ConstraintSystem:193 - The TNM
   'TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx', does not
   directly or indirectly drive any flip-flops, latches and/or RAMs and cannot
   be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo0'.
   If clock manager blocks are directly or indirectly driven, a new TNM
   constraint will not be derived since the referencing constraint is not a
   PERIOD constraint. This TNM is used in the following user group or
   specification:
   <TIMESPEC "TS_CustomFromTo0"= FROM
   "TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 37.1212503750
   ns DATAPATHONLY;> [toplevel_gen.ucf(772)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC "TS_CustomFromTo0"= FROM
   "TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 37.1212503750
   ns DATAPATHONLY;> [toplevel_gen.ucf(772)]

WARNING:ConstraintSystem:193 - The TNM
   'TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx', does not
   directly or indirectly drive any flip-flops, latches and/or RAMs and cannot
   be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo0'.
   If clock manager blocks are directly or indirectly driven, a new TNM
   constraint will not be derived since the referencing constraint is not a
   PERIOD constraint. This TNM is used in the following user group or
   specification:
   <TIMESPEC "TS_CustomFromTo0"= FROM
   "TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 37.1212503750
   ns DATAPATHONLY;> [toplevel_gen.ucf(772)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC "TS_CustomFromTo0"= FROM
   "TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 37.1212503750
   ns DATAPATHONLY;> [toplevel_gen.ucf(772)]

WARNING:ConstraintSystem:193 - The TNM
   'TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx', does not
   directly or indirectly drive any flip-flops, latches and/or RAMs and cannot
   be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo1'.
   If clock manager blocks are directly or indirectly driven, a new TNM
   constraint will not be derived since the referencing constraint is not a
   PERIOD constraint. This TNM is used in the following user group or
   specification:
   <TIMESPEC "TS_CustomFromTo1"= FROM
   "TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(773)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC "TS_CustomFromTo1"= FROM
   "TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(773)]

WARNING:ConstraintSystem:192 - The TNM
   'TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx', does not
   directly or indirectly drive any flip-flops, latches and/or RAMS and cannot
   be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo1'.
   If clock manager blocks are directly or indirectly driven, a new TNM
   constraint will not be derived since the none of the referencing constraints
   are a PERIOD constraint. This TNM is used in the following user groups and/or
   specifications:
   <TIMESPEC "TS_CustomFromTo1"= FROM
   "TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(773)]
   <TIMESPEC "TS_CustomFromTo2"= FROM
   "TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(774)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC "TS_CustomFromTo1"= FROM
   "TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(773)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC "TS_CustomFromTo2"= FROM
   "TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(774)]

WARNING:ConstraintSystem:193 - The TNM
   'TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx', does not
   directly or indirectly drive any flip-flops, latches and/or RAMs and cannot
   be actively used by the referencing MaxDelay constraint 'TS_CustomFromTo2'.
   If clock manager blocks are directly or indirectly driven, a new TNM
   constraint will not be derived since the referencing constraint is not a
   PERIOD constraint. This TNM is used in the following user group or
   specification:
   <TIMESPEC "TS_CustomFromTo2"= FROM
   "TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(774)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC "TS_CustomFromTo2"= FROM
   "TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(774)]

WARNING:ConstraintSystem:193 - The TNM
   'TNM_oSigReturn_n_bushold/*ShiftRegister/SyncBusReset', does not directly or
   indirectly drive any flip-flops, latches and/or RAMs and cannot be actively
   used by the referencing MaxDelay constraint 'TS_CustomFromTo22'. If clock
   manager blocks are directly or indirectly driven, a new TNM constraint will
   not be derived since the referencing constraint is not a PERIOD constraint.
   This TNM is used in the following user group or specification:
   <TIMESPEC "TS_CustomFromTo22"= FROM
   "TNM_oSigReturn_n_bushold/*ShiftRegister/SyncBusReset" TO
   "TNM_iSigOut_msn_bushold/*ShiftRegister/SyncBusReset" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(794)]

WARNING:ConstraintSystem:197 - The following specification is invalid because
   the referenced TNM constraint was removed:
   <TIMESPEC "TS_CustomFromTo22"= FROM
   "TNM_oSigReturn_n_bushold/*ShiftRegister/SyncBusReset" TO
   "TNM_iSigOut_msn_bushold/*ShiftRegister/SyncBusReset" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(794)]

Done...

WARNING:NgdBuild:1212 - User specified non-default attribute value (25.0) was
   detected for the CLKIN_PERIOD attribute on DCM
   "window/NiFpgaStockDcmInst0/DCMx".  This does not match the PERIOD constraint
   value (24.99 ns.).  The uncertainty calculation will use the non-default
   attribute value.  This could result in incorrect uncertainty calculated for
   DCM output clocks.
Checking expanded design ...
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkFifo.NiFpgaFifox/NiFpgaFifoFlagsx/GenDataValidx/DFlopBoolVecx/DFlopSLVx/Ge
   nFlops[2].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.ODataFlop/GenFlops[0].DFlopx
   /FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.ODataFlop/GenFlops[1].DFlopx
   /FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Input.FifoClearController/NiFpgaFifoPortR
   esetx/Crossing.PopToPush/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected
   output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Input.FifoClearController/NiFpgaFifoPortR
   esetx/Crossing.PushToPop/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected
   output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.ODataFlop/GenFlops[1].DFlopx
   /FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.ODataFlop/GenFlops[0].DFlopx
   /FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkFifo.NiFpgaFifox/NiFpgaFifoFlagsx/GenDataValidx/DFlopBoolVecx/DFlopSLVx/Ge
   nFlops[2].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Input.FifoClearController/NiFpgaFifoPortR
   esetx/Crossing.PushToPop/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected
   output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Input.FifoClearController/NiFpgaFifoPortR
   esetx/Crossing.PopToPush/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected
   output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFi
   fo.BlkFifo.Fifox/NiFpgaFifoFlagsx/GenDataValidx/DFlopBoolVecx/DFlopSLVx/GenFl
   ops[4].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Output.FifoClearController/NiFpgaFifoPort
   Resetx/Crossing.PopToPush/PulseSyncBasex/oLocalSigOutx/FDCPEx' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Output.FifoClearController/NiFpgaFifoPort
   Resetx/Crossing.PushToPop/PulseSyncBasex/oLocalSigOutx/FDCPEx' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oPushToggle0_msx/DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.SyncIReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[2].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[3].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[4].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[5].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[6].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[7].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[8].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[9].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[10].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[11].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[12].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[13].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[14].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[15].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[16].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[17].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[18].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[19].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[20].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[21].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[22].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[23].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[24].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[25].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[26].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[27].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[28].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[29].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[30].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[31].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqNum/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncOReset/c2Re
   setFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkOut.SyncOReset/c2
   ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_bushold/MiteClkShifter.ShiftRegister/SyncBusReset/PulseSyncBa
   sex/oLocalSigOutx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_bushold/Clk40Shifter.ShiftRegister/SyncBusReset/PulseSyncBase
   x/oLocalSigOutx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCro
   ssing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex
   /FDCPE_1x' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomain
   Crossing.BusClkToReliableClkHS/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx'
   has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomain
   Crossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEd
   gex/FDCPE_1x' has unconnected output pin
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.SyncOReset/c1NxResetFastLcl" is on the wrong type of object. 
   Please see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncOReset/c1Re
   setFastLcl" is on the wrong type of object.  Please see the Constraints Guide
   for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkOut.SyncOReset/c1
   ResetFastLcl" is on the wrong type of object.  Please see the Constraints
   Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
INFO:TclTasksC:1850 - process run : Translate is done.
   "window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCro
   ssing.BusClkToReliableClkHS/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong
   type of object.  Please see the Constraints Guide for more information on
   this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomain
   Crossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c1ResetFastLcl" is on the
   wrong type of object.  Please see the Constraints Guide for more information
   on this attribute.
WARNING:NgdBuild:470 - bidirect pad net 'temp_miso' has no legal driver

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:    15
  Number of warnings:  96

Total REAL time to NGDBUILD completion: 1 min  21 sec
Total CPU time to NGDBUILD completion:  1 min  9 sec

One or more errors were found during NGDBUILD.  No NGD file will be written.

Writing NGDBUILD log file "toplevel_gen.bld"...

Process "Translate" failed
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Adapter16.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_246.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_27.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataRd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataWr.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio80MhzClkRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9205ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9208IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213FxpScaleData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Initializer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SampleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResourceLogic.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ClockCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ErrorDecode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223HseioReadHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoNodeResHolder.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleSerializer.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleValidDelay.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403CommHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DiIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DioHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DoIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403LdHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SpiWord.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeDetection.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeIdentification.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCrcCheck.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiEeprom.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInitSequence.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInputFlops.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelectorControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiOutputMuxes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPicoBeatleInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPinConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPulseMask.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioClockCondition.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioParallelCrcCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioSourceSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForAnsteuerung_beenden_ctl_0RHFpgaRe
   adPortOnResbushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForMiteIoLikePortOnResInterface.vhd"
   into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTmax_ctl_5RHFpgaReadPortOnResbush
   old.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTopEnablesPortOnResTopEnablePassT
   hru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbFordinPortOnResSleep.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolVec.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSlvResetVal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopUnsigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DiagramReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaDisabler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteReadRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteWriteRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncAsyncInBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBoolAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSlAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainSM.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainWithTimeout.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FeedbackNonSctlCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoReadAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoWriteAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FloatingFeedbackGInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpAddSub.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivPreproc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivRnd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivSigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDynamicShift.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpNormalize.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpShiftCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/GenDataValid.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBaseResetCross.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/IDSel_Timer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Interface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/InvisibleResholder.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponent.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponentEnableChain.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaInput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaOutput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterfaceOutputEnables.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteIrq.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteReadInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteWriteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000001_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000012_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000020_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructure_64.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002e_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000032_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000041_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000042_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000004b_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000058_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000059_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005a_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005c_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000082_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008e_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008f_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000091_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000092_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000ac_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000bc_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000de_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000df_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e1_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e2_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e9_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000fb_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000010d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_Speichern4_dash_2FPGA.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbDelayer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbPowerOf2.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbRW.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbSerializeAccess.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOpNot.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaClockManagerControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaCtrlIndRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam_Inferred.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoClearControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoCountControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPopBuffer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPortReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFlipFlopFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaHostAccessibleRegister.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderRead.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderWrite.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLoopTimer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMergeErrors.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteReadInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteWriteInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPipelinedOrGateTreeSlv.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPulseSyncBaseWrapper.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegFrameworkShiftReg.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCoreBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaShiftReg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleModuloCounter.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaStockDcm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFixedToFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompareCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivideCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiplyCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixed.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixedCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandlerSlv.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiCycleEnableHandler.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFixedPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFloatingPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToInteger.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Divide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Equal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Greater.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32GreaterOrEqual.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Less.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32LessOrEqual.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Multiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32NotEqual.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommIntConfiguration.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommunicationInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9211Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9223Shared.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9403IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpArithmetic.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaArbiter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaCoresFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifoGenericValue.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaIrqRegisters.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaViControlRegister.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiLvPrims.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess32.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ResetSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SafeBusCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Sleep.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrInd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrIndOpt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SyncFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TheWindow.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TimeoutManager.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TopEnablePassThru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViSignature.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_132.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_173.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_185.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_189.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_202.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_136.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_175.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_187.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_232.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/bushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CommSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205ControlSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GenScanLine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SetTriggers.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SettingRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_SyncRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_io.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalReciprocal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMemory.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalParallelCrc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStock.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModuleId.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/forloop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_r_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_w_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMaxArray_vi_colon_Clone0.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMinArray_vi.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/whileloop.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Adapter16.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_246.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_27.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataRd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataWr.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio80MhzClkRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9205ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9208IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213FxpScaleData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Initializer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SampleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResourceLogic.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ClockCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ErrorDecode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223HseioReadHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoNodeResHolder.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleSerializer.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleValidDelay.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403CommHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DiIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DioHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DoIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403LdHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SpiWord.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeDetection.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeIdentification.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCrcCheck.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiEeprom.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInitSequence.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInputFlops.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelectorControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiOutputMuxes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPicoBeatleInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPinConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPulseMask.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioClockCondition.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioParallelCrcCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioSourceSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForAnsteuerung_beenden_ctl_0RHFpgaRe
   adPortOnResbushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForMiteIoLikePortOnResInterface.vhd"
   into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTmax_ctl_5RHFpgaReadPortOnResbush
   old.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTopEnablesPortOnResTopEnablePassT
   hru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbFordinPortOnResSleep.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolVec.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSlvResetVal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopUnsigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DiagramReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaDisabler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteReadRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteWriteRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncAsyncInBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBoolAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSlAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainSM.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainWithTimeout.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FeedbackNonSctlCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoReadAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoWriteAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FloatingFeedbackGInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpAddSub.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivPreproc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivRnd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivSigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDynamicShift.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpNormalize.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpShiftCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/GenDataValid.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBaseResetCross.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/IDSel_Timer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Interface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/InvisibleResholder.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponent.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponentEnableChain.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaInput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaOutput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterfaceOutputEnables.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteIrq.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteReadInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteWriteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000001_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000012_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000020_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructure_64.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002e_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000032_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000041_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000042_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000004b_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000058_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000059_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005a_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005c_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000082_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008e_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008f_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000091_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000092_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000ac_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000bc_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000de_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000df_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e1_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e2_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e9_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000fb_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000010d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_Speichern4_dash_2FPGA.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbDelayer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbPowerOf2.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbRW.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbSerializeAccess.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOpNot.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaClockManagerControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaCtrlIndRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam_Inferred.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoClearControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoCountControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPopBuffer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPortReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFlipFlopFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaHostAccessibleRegister.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderRead.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderWrite.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLoopTimer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMergeErrors.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteReadInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteWriteInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPipelinedOrGateTreeSlv.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPulseSyncBaseWrapper.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegFrameworkShiftReg.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCoreBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaShiftReg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleModuloCounter.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaStockDcm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFixedToFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompareCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivideCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiplyCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixed.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixedCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandlerSlv.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiCycleEnableHandler.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFixedPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFloatingPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToInteger.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Divide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Equal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Greater.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32GreaterOrEqual.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Less.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32LessOrEqual.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Multiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32NotEqual.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommIntConfiguration.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommunicationInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9211Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9223Shared.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9403IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpArithmetic.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaArbiter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaCoresFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifoGenericValue.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaIrqRegisters.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaViControlRegister.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiLvPrims.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess32.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ResetSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SafeBusCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Sleep.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrInd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrIndOpt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SyncFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TheWindow.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TimeoutManager.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TopEnablePassThru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViSignature.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_132.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_173.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_185.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_189.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_202.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_136.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_175.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_187.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_232.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/bushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CommSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205ControlSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GenScanLine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SetTriggers.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SettingRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_SyncRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_io.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalReciprocal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMemory.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalParallelCrc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStock.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModuleId.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/forloop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_r_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_w_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMaxArray_vi_colon_Clone0.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMinArray_vi.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/whileloop.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Adapter16.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_246.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_27.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataRd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataWr.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio80MhzClkRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9205ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9208IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213FxpScaleData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Initializer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SampleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResourceLogic.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ClockCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ErrorDecode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223HseioReadHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoNodeResHolder.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleSerializer.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleValidDelay.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403CommHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DiIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DioHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DoIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403LdHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SpiWord.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeDetection.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeIdentification.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCrcCheck.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiEeprom.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInitSequence.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInputFlops.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelectorControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiOutputMuxes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPicoBeatleInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPinConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPulseMask.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioClockCondition.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioParallelCrcCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioSourceSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForAnsteuerung_beenden_ctl_0RHFpgaRe
   adPortOnResbushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForMiteIoLikePortOnResInterface.vhd"
   into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTmax_ctl_5RHFpgaReadPortOnResbush
   old.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTopEnablesPortOnResTopEnablePassT
   hru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbFordinPortOnResSleep.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolVec.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSlvResetVal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopUnsigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DiagramReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaDisabler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteReadRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteWriteRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncAsyncInBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBoolAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSlAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainSM.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainWithTimeout.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FeedbackNonSctlCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoReadAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoWriteAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FloatingFeedbackGInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpAddSub.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivPreproc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivRnd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivSigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDynamicShift.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpNormalize.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpShiftCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/GenDataValid.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBaseResetCross.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/IDSel_Timer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Interface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/InvisibleResholder.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponent.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponentEnableChain.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaInput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaOutput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterfaceOutputEnables.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteIrq.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteReadInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteWriteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000001_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000012_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000020_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructure_64.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002e_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000032_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000041_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000042_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000004b_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000058_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000059_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005a_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005c_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000082_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008e_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008f_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000091_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000092_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000ac_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000bc_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000de_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000df_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e1_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e2_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e9_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000fb_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000010d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_Speichern4_dash_2FPGA.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbDelayer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbPowerOf2.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbRW.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbSerializeAccess.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOpNot.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaClockManagerControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaCtrlIndRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam_Inferred.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoClearControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoCountControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPopBuffer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPortReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFlipFlopFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaHostAccessibleRegister.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderRead.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderWrite.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLoopTimer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMergeErrors.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteReadInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteWriteInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPipelinedOrGateTreeSlv.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPulseSyncBaseWrapper.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegFrameworkShiftReg.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCoreBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaShiftReg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleModuloCounter.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaStockDcm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFixedToFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompareCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivideCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiplyCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixed.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixedCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandlerSlv.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiCycleEnableHandler.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFixedPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFloatingPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToInteger.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Divide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Equal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Greater.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32GreaterOrEqual.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Less.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32LessOrEqual.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Multiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32NotEqual.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommIntConfiguration.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommunicationInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9211Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9223Shared.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9403IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpArithmetic.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaArbiter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaCoresFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifoGenericValue.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaIrqRegisters.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaViControlRegister.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiLvPrims.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess32.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ResetSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SafeBusCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Sleep.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrInd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrIndOpt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SyncFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TheWindow.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TimeoutManager.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TopEnablePassThru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViSignature.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_132.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_173.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_185.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_189.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_202.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_136.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_175.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_187.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_232.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/bushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CommSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205ControlSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GenScanLine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SetTriggers.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SettingRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_SyncRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_io.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalReciprocal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMemory.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalParallelCrc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStock.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModuleId.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/forloop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_r_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_w_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMaxArray_vi_colon_Clone0.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMinArray_vi.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/whileloop.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl

Started : "Translate".
Running ngdbuild...
Command Line: ngdbuild -intstyle ise -dd _ngo -aul -nt timestamp -u -uc toplevel_gen.ucf -p xc5vlx30-ff676-1 toplevel_gen.ngc toplevel_gen.ngd

Command Line: C:\NIFPGA\programs\Xilinx13_4\ISE\bin\nt\unwrapped\ngdbuild.exe
-intstyle ise -dd _ngo -aul -nt timestamp -u -uc toplevel_gen.ucf -p
xc5vlx30-ff676-1 toplevel_gen.ngc toplevel_gen.ngd

Reading NGO file "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.ngc" ...
Loading design module
"C:\NIFPGA\jobs\G2K2D0O_KSw9nkc/NiLvXipFloat32Divide.ngc"...
Loading design module
"C:\NIFPGA\jobs\G2K2D0O_KSw9nkc/NiLvXipFloat32Multiply.ngc"...
Gathering constraint information from source properties...
Done.

Annotating constraints to design from ucf file "toplevel_gen.ucf" ...
Resolving constraint associations...
Checking Constraint Associations...
WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoAddr<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoDmaAck_n<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoRd_n'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoWt_n'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromAddrDackIorIowRamsel"= "mIoAddr<*>" "mIoDmaAck_n<*>" "mIoRd_n"
   "mIoWt_n" "mIoRamSel_n";> [toplevel_gen.ucf(712)]: Unable to find an active
   'TNM' or 'TimeGrp' constraint named 'mIoRamSel_n'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromDataAddrDackIorIowRamsel"= "mIoData<*>"
   "AsyncFromAddrDackIorIowRamsel";> [toplevel_gen.ucf(713)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'mIoData<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP
   "AsyncFromDataAddrDackIorIowRamsel"= "mIoData<*>"
   "AsyncFromAddrDackIorIowRamsel";> [toplevel_gen.ucf(713)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'AsyncFromAddrDackIorIowRamsel'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtk"= "aIoInt*"
   "mIoDmaReq<*>" "mIoDtack_n";> [toplevel_gen.ucf(714)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'aIoInt*'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtk"= "aIoInt*"
   "mIoDmaReq<*>" "mIoDtack_n";> [toplevel_gen.ucf(714)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'mIoDmaReq<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtk"= "aIoInt*"
   "mIoDmaReq<*>" "mIoDtack_n";> [toplevel_gen.ucf(714)]: Unable to find an
   active 'TNM' or 'TimeGrp' constraint named 'mIoDtack_n'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtkRdyData"=
   "AsyncToIrqDrqDtk" "mIoReady" "mIoData<*>";> [toplevel_gen.ucf(715)]: Unable
   to find an active 'TNM' or 'TimeGrp' constraint named 'AsyncToIrqDrqDtk'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtkRdyData"=
   "AsyncToIrqDrqDtk" "mIoReady" "mIoData<*>";> [toplevel_gen.ucf(715)]: Unable
   to find an active 'TNM' or 'TimeGrp' constraint named 'mIoReady'.

WARNING:ConstraintSystem:56 - Constraint <TIMEGRP "AsyncToIrqDrqDtkRdyData"=
   "AsyncToIrqDrqDtk" "mIoReady" "mIoData<*>";> [toplevel_gen.ucf(715)]: Unable
   to find an active 'TNM' or 'TimeGrp' constraint named 'mIoData<*>'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo0"= FROM
   "TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 37.1212503750
   ns DATAPATHONLY;> [toplevel_gen.ucf(772)]: Unable to find an active 'TimeGrp'
   or 'TNM' or 'TPSync' constraint named
   'TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo0"= FROM
   "TNM_iHoldSigIn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 37.1212503750
   ns DATAPATHONLY;> [toplevel_gen.ucf(772)]: Unable to find an active 'TimeGrp'
   or 'TNM' or 'TPSync' constraint named
   'TNM_oHoldSigIn_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo1"= FROM
   "TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(773)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo1"= FROM
   "TNM_oSigReturn_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(773)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo2"= FROM
   "TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(774)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo2"= FROM
   "TNM_oLocalSigOutCE_Crio9220Resource4/*/PulseSyncIdSelTimerTickx" TO
   "TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(774)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_iSigOut_msCrio9220Resource4/*/PulseSyncIdSelTimerTickx'.

WARNING:ConstraintSystem:56 - Constraint <TIMESPEC "TS_CustomFromTo22"= FROM
   "TNM_oSigReturn_n_bushold/*ShiftRegister/SyncBusReset" TO
   "TNM_iSigOut_msn_bushold/*ShiftRegister/SyncBusReset" 74.2425007499 ns
   DATAPATHONLY;> [toplevel_gen.ucf(794)]: Unable to find an active 'TimeGrp' or
   'TNM' or 'TPSync' constraint named
   'TNM_oSigReturn_n_bushold/*ShiftRegister/SyncBusReset'.


Done...

WARNING:NgdBuild:1212 - User specified non-default attribute value (25.0) was
   detected for the CLKIN_PERIOD attribute on DCM
   "window/NiFpgaStockDcmInst0/DCMx".  This does not match the PERIOD constraint
   value (24.99 ns.).  The uncertainty calculation will use the non-default
   attribute value.  This could result in incorrect uncertainty calculated for
   DCM output clocks.
Checking expanded design ...
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkFifo.NiFpgaFifox/NiFpgaFifoFlagsx/GenDataValidx/DFlopBoolVecx/DFlopSLVx/Ge
   nFlops[2].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.ODataFlop/GenFlops[0].DFlopx
   /FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.ODataFlop/GenFlops[1].DFlopx
   /FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Input.FifoClearController/NiFpgaFifoPortR
   esetx/Crossing.PopToPush/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected
   output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[0].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Input.FifoClearController/NiFpgaFifoPortR
   esetx/Crossing.PushToPop/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected
   output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.ODataFlop/GenFlops[1].DFlopx
   /FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkOverflow.HandshakeBoolx/HandshakeBasex/BlkOut.ODataFlop/GenFlops[0].DFlopx
   /FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.
   BlkFifo.NiFpgaFifox/NiFpgaFifoFlagsx/GenDataValidx/DFlopBoolVecx/DFlopSLVx/Ge
   nFlops[2].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Input.FifoClearController/NiFpgaFifoPortR
   esetx/Crossing.PushToPop/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected
   output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Input.FifoClearController/NiFpgaFifoPortR
   esetx/Crossing.PopToPush/PulseSyncBasex/oLocalSigOutx/FDCPEx' has unconnected
   output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaCha
   nnel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFi
   fo.BlkFifo.Fifox/NiFpgaFifoFlagsx/GenDataValidx/DFlopBoolVecx/DFlopSLVx/GenFl
   ops[4].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Output.FifoClearController/NiFpgaFifoPort
   Resetx/Crossing.PopToPush/PulseSyncBasex/oLocalSigOutx/FDCPEx' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaCha
   nnel.MiteDmaComponentx/EnableChains/Output.FifoClearController/NiFpgaFifoPort
   Resetx/Crossing.PushToPop/PulseSyncBasex/oLocalSigOutx/FDCPEx' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oPushToggle0_msx/DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.SyncIReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[1].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[2].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[3].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[4].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[5].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[6].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[7].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[8].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[9].DFlopx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[10].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[11].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[12].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[13].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[14].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[15].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[16].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[17].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[18].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[19].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[20].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[21].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[22].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[23].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[24].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[25].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[26].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[27].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[28].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[29].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[30].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.oDataFlopx/GenFlops[31].DFlopx/FDCPEx' has unconnected output
   pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqNum/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has
   unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncOReset/c2Re
   setFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkOut.SyncOReset/c2
   ResetFe_msx/DFlopFallingEdgex/FDCPE_1x' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_bushold/MiteClkShifter.ShiftRegister/SyncBusReset/PulseSyncBa
   sex/oLocalSigOutx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/n_bushold/Clk40Shifter.ShiftRegister/SyncBusReset/PulseSyncBase
   x/oLocalSigOutx/FDCPEx' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCro
   ssing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEdgex
   /FDCPE_1x' has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomain
   Crossing.BusClkToReliableClkHS/BlkOut.oDataFlopx/GenFlops[0].DFlopx/FDCPEx'
   has unconnected output pin
WARNING:NgdBuild:440 - FF primitive
   'window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomain
   Crossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c2ResetFe_msx/DFlopFallingEd
   gex/FDCPE_1x' has unconnected output pin
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/n_Interface/MiteInterfacex/IrqComponents[0].MiteIrqx/HandShakeI
   rqAck/BlkOut.SyncOReset/c1NxResetFastLcl" is on the wrong type of object. 
   Please see the Constraints Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/n_bushold/Clk40Crossing.Clk40ToInterface/BlkOut.SyncOReset/c1Re
   setFastLcl" is on the wrong type of object.  Please see the Constraints Guide
INFO:TclTasksC:1850 - process run : Translate is done.
   for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/n_bushold/Clk40Crossing.Clk40FromInterface/BlkOut.SyncOReset/c1
   ResetFastLcl" is on the wrong type of object.  Please see the Constraints
   Guide for more information on this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/ViControlx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomainCro
   ssing.BusClkToReliableClkHS/BlkOut.SyncOReset/c1ResetFastLcl" is on the wrong
   type of object.  Please see the Constraints Guide for more information on
   this attribute.
WARNING:NgdBuild:483 - Attribute "INIT" on
   "window/theVI/DiagramResetx/HostWtAccessBlk.BusClkToReliableClkHS/ClockDomain
   Crossing.BusClkToReliableClkHS/BlkOut.SyncOReset/c1ResetFastLcl" is on the
   wrong type of object.  Please see the Constraints Guide for more information
   on this attribute.
WARNING:NgdBuild:470 - bidirect pad net 'temp_miso' has no legal driver

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

NGDBUILD Design Results Summary:
  Number of errors:     0
  Number of warnings:  83

Writing NGD file "toplevel_gen.ngd" ...
Total REAL time to NGDBUILD completion: 1 min  16 sec
Total CPU time to NGDBUILD completion:  1 min  10 sec

Writing NGDBUILD log file "toplevel_gen.bld"...

NGDBUILD done.

Process "Translate" completed successfully
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Adapter16.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_246.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ArrayIndexNode_27.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataRd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CpuDataWr.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio80MhzClkRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9205ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9208IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9211SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213FxpScaleData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9213UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Initializer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SampleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9220SyncResourceLogic.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ClockCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223ErrorDecode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223HseioReadHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223IoNodeResHolder.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleSerializer.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9223SampleValidDelay.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9264SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403CommHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DiIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DioHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403DoIoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403LdHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403ResourceCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SpiWord.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Crio9403SyncResource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeDetection.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCartridgeIdentification.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiCrcCheck.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiEeprom.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInitSequence.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiInputFlops.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiModeSelectorControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiOutputMuxes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPicoBeatleInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPinConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiPulseMask.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiConfig.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCiSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioClockCondition.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioParallelCrcCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CrioSourceSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForAnsteuerung_beenden_ctl_0RHFpgaRe
   adPortOnResbushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForMiteIoLikePortOnResInterface.vhd"
   into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTmax_ctl_5RHFpgaReadPortOnResbush
   old.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbForTopEnablesPortOnResTopEnablePassT
   hru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/CustomArbFordinPortOnResSleep.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopBoolVec.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopFallingEdge.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopSlvResetVal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DFlopUnsigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DiagramReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaDisabler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteReadRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DmaMiteWriteRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncAsyncInBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncBoolAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/DoubleSyncSlAsyncIn.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainSM.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/EnableChainWithTimeout.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FeedbackNonSctlCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoReadAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FifoWriteAdapter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FloatingFeedbackGInit.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpAddSub.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivPreproc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivRnd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDivSigned.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpDynamicShift.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpNormalize.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/FxpShiftCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/GenDataValid.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBaseResetCross.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/HandshakeSLV.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/IDSel_Timer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Interface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/InvisibleResholder.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponent.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaComponentEnableChain.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaInput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteDmaOutput.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteInterfaceOutputEnables.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteIrq.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteReadInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/MiteWriteInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000000_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000001_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000012_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000013_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000020_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000021_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0000.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructureFrame_0001.vhd
   " into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002d_CaseStructure_64.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000002e_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000032_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000041_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000042_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000004b_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000058_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000059_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005a_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005c_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000005d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000082_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008e_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000008f_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000091_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_00000092_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000ac_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000b8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000bc_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c0_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c4_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000c8_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000de_WhileLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000df_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e1_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e2_ForLoop.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000e9_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_000000fb_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_0000010d_SequenceFrame.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaAG_Speichern4_dash_2FPGA.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbDelayer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbPowerOf2.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbRW.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaArbSerializeAccess.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaBoolOpNot.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaClockManagerControl.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaCtrlIndRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaDualPortRam_Inferred.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoClearControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoCountControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPopBuffer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFifoPortReset.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaFlipFlopFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaHostAccessibleRegister.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderRead.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLocalResHolderWrite.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaLoopTimer.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMergeErrors.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteReadInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaMiteWriteInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPipelinedOrGateTreeSlv.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaPulseSyncBaseWrapper.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegFrameworkShiftReg.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaRegisterCoreBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaShiftReg.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleCounter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaSimpleModuloCounter.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiFpgaStockDcm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFixedToFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatCompareCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatDivideCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatMultiplyCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixed.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFloatToFixedCore.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCoerce.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpCompare.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpEnableHandlerSlv.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiCycleEnableHandler.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvFxpMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFixedPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToFloatingPoint.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvToInteger.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Divide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Equal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Greater.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32GreaterOrEqual.vhd" into
   library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Less.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32LessOrEqual.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32Multiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/NiLvXipFloat32NotEqual.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommIntConfiguration.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCommunicationInterface.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9211Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9213Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9220Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9223Shared.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrio9403IoNode.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCiHsiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioCommInt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgCrioInterface.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFloat.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpArithmetic.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgFxpDivide.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgGray.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaArbiter.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaBoolOp.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaCoresFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifo.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaFifoGenericValue.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaIrqRegisters.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiFpgaViControlRegister.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiLvPrims.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgNiUtilities.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgRegister.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9205Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9211.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PkgcRio9264Cal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBase.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncBool.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/PulseSyncSL.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/RegisterAccess32.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ResetSync.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SafeBusCrossing.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/Sleep.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrInd.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SubVICtlOrIndOpt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/SyncFifoFlags.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TheWindow.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TimeoutManager.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/TopEnablePassThru.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViControl.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/ViSignature.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_132.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_173.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_185.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_189.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arrayLpIndx_202.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_136.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_175.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_187.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/arraycollect_232.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/bushold.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205CommSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205ControlSm.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GenScanLine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SetTriggers.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205SettingRegs.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_Resource.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_SyncRes.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9205_io.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalData.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264CalReciprocal.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264EnableChainHandler.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264GetCalConst.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264IoHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRio9264UpdateHandler.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMemory.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalMultiply.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioCalParallelCrc.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStock.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockEepromRead.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModeSelector.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockModuleId.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/cRioStockSpiEngine.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/forloop.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_r_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/resholder_w_opt.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMaxArray_vi_colon_Clone0.vhd" into library
   work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/subMinArray_vi.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/toplevel_gen.vhd" into library work
INFO:HDLCompiler:1061 - Parsing VHDL file
   "C:/NIFPGA/jobs/G2K2D0O_KSw9nkc/whileloop.vhd" into library work
INFO:ProjectMgmt - Parsing design hierarchy completed successfully.
WARNING:ProjectMgmt - Circular Reference:
   work:Architecture|NiFpgaPipelinedOrGateTreeSlv|rtl

Started : "Map".
Running map...
Command Line: map -intstyle ise -p xc5vlx30-ff676-1 -w -logic_opt off -ol high -xe n -t 1 -register_duplication off -global_opt off -mt off -cm area -ir off -pr off -lc off -power off -o toplevel_gen_map.ncd toplevel_gen.ngd toplevel_gen.pcf
Using target part "5vlx30ff676-1".
vvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvvv
INFO:Security:50 - The XILINXD_LICENSE_FILE environment variable is set to
'C:\NIFPGA\programs\Xilinx13_4\ISE\data\lvfpgalicense.lic'.
INFO:Security:52 - The LM_LICENSE_FILE environment variable is set to
'C:\NIFPGA\programs\Xilinx13_4\ISE\data\lvfpgalicense.lic'.
INFO:Security:54 - 'xc5vlx30' is a WebPack part.
WARNING:Security:43 - No license file was found in the standard Xilinx license
directory.
WARNING:Security:44 - Since no license file was found,
       please run the Xilinx License Configuration Manager
       (xlcm or "Manage Xilinx Licenses")
       to assist in obtaining a license.
WARNING:Security:42 - Your software subscription period has lapsed. Your current
version of Xilinx tools will continue to function, but you no longer qualify for
Xilinx software updates or new releases.
----------------------------------------------------------------------
Mapping design into LUTs...
WARNING:MapLib:701 - Signal dio12 connected to top level port dio12 has been
   removed.
WARNING:MapLib:701 - Signal dio16 connected to top level port dio16 has been
   removed.
WARNING:MapLib:701 - Signal dio22 connected to top level port dio22 has been
   removed.
WARNING:MapLib:701 - Signal dio26 connected to top level port dio26 has been
   removed.
WARNING:MapLib:701 - Signal dio29 connected to top level port dio29 has been
   removed.
WARNING:MapLib:701 - Signal dio36 connected to top level port dio36 has been
   removed.
WARNING:MapLib:701 - Signal dio39 connected to top level port dio39 has been
   removed.
WARNING:MapLib:701 - Signal dio42 connected to top level port dio42 has been
   removed.
WARNING:MapLib:701 - Signal dio49 connected to top level port dio49 has been
   removed.
WARNING:MapLib:701 - Signal dio52 connected to top level port dio52 has been
   removed.
WARNING:MapLib:701 - Signal dio56 connected to top level port dio56 has been
   removed.
WARNING:MapLib:701 - Signal dio62 connected to top level port dio62 has been
   removed.
WARNING:MapLib:701 - Signal dio66 connected to top level port dio66 has been
   removed.
WARNING:MapLib:701 - Signal dio72 connected to top level port dio72 has been
   removed.
WARNING:MapLib:701 - Signal dio76 connected to top level port dio76 has been
   removed.
WARNING:MapLib:40 - The offset specification "OFFSET=IN 10000 pS VALID 20000 pS
   BEFORE Clk40" on net "dio42" has been discarded, because the net was
   optimized out of the design.
WARNING:MapLib:40 - The offset specification "OFFSET=IN 10000 pS VALID 20000 pS
   BEFORE Clk40" on net "dio49" has been discarded, because the net was
   optimized out of the design.
WARNING:MapLib:40 - The offset specification "OFFSET=IN 3000 pS VALID 7000 pS
   BEFORE Clk40" on net "dio56" has been discarded, because the net was
   optimized out of the design.
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM1
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM1_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM1
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM1_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM1
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM1_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM1
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM1_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM10
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM10_REGCLKAU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM10
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM10_REGCLKAL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM10
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM10_REGCLKBU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM10
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM10_REGCLKBL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM11
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM11_REGCLKAU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM11
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM11_REGCLKAL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM11
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM11_REGCLKBU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM11
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM11_REGCLKBL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM12
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM12_REGCLKAU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM12
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM12_REGCLKAL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM12
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM12_REGCLKBU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM12
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM12_REGCLKBL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM13
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM13_REGCLKAU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM13
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM13_REGCLKAL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM13
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM13_REGCLKBU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM13
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM13_REGCLKBL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM14
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM14_REGCLKAU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM14
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM14_REGCLKAL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM14
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM14_REGCLKBU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM14
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM14_REGCLKBL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM15
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM15_REGCLKAU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM15
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM15_REGCLKAL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM15
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM15_REGCLKBU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM15
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM15_REGCLKBL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM16
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM16_REGCLKAU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM16
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM16_REGCLKAL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM16
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM16_REGCLKBU_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM16
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM16_REGCLKBL_tiesi
   g
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM2
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM2_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM2
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM2_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM2
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM2_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM2
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM2_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM3
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM3_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM3
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM3_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM3
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM3_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM3
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM3_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM4
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM4_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM4
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM4_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM4
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM4_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM4
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM4_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM5
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM5_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM5
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM5_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM5
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM5_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM5
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM5_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM6
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM6_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM6
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM6_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM6
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM6_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM6
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM6_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM7
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM7_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM7
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM7_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM7
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM7_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM7
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM7_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM8
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM8_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM8
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM8_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM8
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM8_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM8
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM8_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM9
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM9_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM9
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM9_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM9
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM9_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM9
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[1].GenNiFpgaChan
   nel.MiteDmaComponentx/GenInput.DmaInputx/NiFpgaMiteReadInterfacex/BlkAiFifo.B
   lkFifo.NiFpgaFifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM9_REGCLKBL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChan
   nel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFif
   o.BlkFifo.Fifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM
   of frag REGCLKAU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChan
   nel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFif
   o.BlkFifo.Fifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM_REGCLKAU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChan
   nel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFif
   o.BlkFifo.Fifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM
   of frag REGCLKAL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChan
   nel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFif
   o.BlkFifo.Fifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM_REGCLKAL_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChan
   nel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFif
   o.BlkFifo.Fifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM
   of frag REGCLKBU connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChan
   nel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFif
   o.BlkFifo.Fifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM_REGCLKBU_tiesig
WARNING:Pack:2874 - Trimming timing constraints from pin
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChan
   nel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFif
   o.BlkFifo.Fifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM
   of frag REGCLKBL connected to power/ground net
   window/theVI/n_Interface/MiteInterfacex/DmaBlk.DmaComponents[2].GenNiFpgaChan
   nel.MiteDmaComponentx/GenOutput.DmaOutputx/NiFpgaMiteWriteInterfacex/BlkAoFif
   o.BlkFifo.Fifox/NiFpgaDualPortRamx/InferredRamx/Mram_iRAM_REGCLKBL_tiesig
Running directed packing...
WARNING:Pack:2549 - The register
   "window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205Cont
   rolSmx/cIdOutputsEn" has the property IOB=TRUE, but was not packed into the
   OLOGIC component. The register
   window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205Contr
   olSmx/cIdOutputsEn can not use TFF because the clock signal does not agree
   with register
   window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205CommS
   mx/cSpiCs_n.
WARNING:Pack:2549 - The register
   "window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/Mod
   eSelector/cEeOutputsEn" has the property IOB=TRUE, but was not packed into
   the OLOGIC component. The register
   window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/Mode
   Selector/cEeOutputsEn can not use TFF because the clock signal does not agree
   with register
   window/theVI/Crio9264Resource6/Crio9264ResourceCorex/cRio9264x/cRioStock/SpiE
   ngine/cCs_n.
WARNING:Pack:2549 - The register
   "window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205Cont
   rolSmx/cConvEn" has the property IOB=TRUE, but was not packed into the OLOGIC
   component. The register
   window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205Contr
   olSmx/cConvEn can not use TFF because the clock signal does not agree with
   register
   window/theVI/cRio9205_Resource5/Crio9205ResourceCorex/cRio9205x/cRio9205CommS
   mx/cConv_n.
WARNING:Pack:2515 - The LUT-1 inverter "window/dio05_dout_inv1_INV_0" failed to
   join the OLOGIC comp matched to output buffer "dio05_OBUFT".  This may result
   in suboptimal timing.  The LUT-1 inverter window/dio05_dout_inv1_INV_0 drives
   multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_10_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_11_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_12_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_20_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_13_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_21_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_14_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_22_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_30_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_15_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_23_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_31_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_16_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_24_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_17_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_25_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_18_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_26_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_19_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_27_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_28_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_29_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_0_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_1_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_2_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_3_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_4_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_5_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_6_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_7_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_8_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
WARNING:Pack:2515 - The LUT-1 inverter "mIoDataOE_inv321_INV_0" failed to join
   the OLOGIC comp matched to output buffer "mIoData_9_IOBUF/OBUFT".  This may
   result in suboptimal timing.  The LUT-1 inverter mIoDataOE_inv321_INV_0
   drives multiple loads.
Running delay-based LUT packing...
Updating timing models...
WARNING:Timing:3175 - Clk40 does not clock data from dio46
WARNING:Timing:3225 - Timing constraint COMP "dio46" OFFSET = IN 3 ns VALID 7 ns
   BEFORE COMP "Clk40" ignored during timing analysis
WARNING:Timing:3175 - MiteClk does not clock data to mIoDmaReq<3>
WARNING:Timing:3225 - Timing constraint COMP "mIoDmaReq<3>" OFFSET = OUT 15.46
   ns AFTER COMP "MiteClk" ignored during timing analysis
WARNING:Timing:3175 - MiteClk does not clock data from mIoAddr<1>
WARNING:Timing:3225 - Timing constraint COMP "mIoAddr<1>" OFFSET = IN 12 ns
INFO:TclTasksC:1850 - process run : Map is done.
   VALID 12 ns BEFORE COMP "MiteClk" ignored during timing analysis
WARNING:Timing:3175 - MiteClk does not clock data from mIoAddr<0>
WARNING:Timing:3225 - Timing constraint COMP "mIoAddr<0>" OFFSET = IN 12 ns
   VALID 12 ns BEFORE COMP "MiteClk" ignored during timing analysis
INFO:Map:215 - The Interim Design Summary has been generated in the MAP Report
   (.mrp).
Running timing-driven placement...
Total REAL time at the beginning of Placer: 1 mins 44 secs 
Total CPU  time at the beginning of Placer: 1 mins 22 secs 

Phase 1.1  Initial Placement Analysis
Phase 1.1  Initial Placement Analysis (Checksum:881a0b7b) REAL time: 1 mins 48 secs 

Phase 2.7  Design Feasibility Check
Phase 2.7  Design Feasibility Check (Checksum:881a0b7b) REAL time: 1 mins 48 secs 

Phase 3.31  Local Placement Optimization
Phase 3.31  Local Placement Optimization (Checksum:881a0b7b) REAL time: 1 mins 48 secs 

Phase 4.37  Local Placement Optimization
Phase 4.37  Local Placement Optimization (Checksum:881a0b7b) REAL time: 1 mins 48 secs 

Phase 5.33  Local Placement Optimization
Phase 5.33  Local Placement Optimization (Checksum:881a0b7b) REAL time: 2 mins 13 secs 

Phase 6.32  Local Placement Optimization
Phase 6.32  Local Placement Optimization (Checksum:881a0b7b) REAL time: 2 mins 14 secs 

Phase 7.2  Initial Clock and IO Placement

Phase 7.2  Initial Clock and IO Placement (Checksum:6212f182) REAL time: 2 mins 19 secs 

Phase 8.36  Local Placement Optimization
Phase 8.36  Local Placement Optimization (Checksum:6212f182) REAL time: 2 mins 19 secs 

Phase 9.30  Global Clock Region Assignment
Phase 9.30  Global Clock Region Assignment (Checksum:6212f182) REAL time: 2 mins 19 secs 

Phase 10.3  Local Placement Optimization
Phase 10.3  Local Placement Optimization (Checksum:6212f182) REAL time: 2 mins 19 secs 

Phase 11.5  Local Placement Optimization
Phase 11.5  Local Placement Optimization (Checksum:6212f182) REAL time: 2 mins 20 secs 

Phase 12.8  Global Placement
........................
........................................................................................................
.........................................................................
Fitter failed. Exiting placer.
Phase 12.8  Global Placement (Checksum:2e0b991e) REAL time: 3 mins 58 secs 

Total REAL time to Placer completion: 3 mins 58 secs 
Total CPU  time to Placer completion: 3 mins 36 secs 
ERROR:Pack:1654 - The timing-driven placement phase encountered an error.

Mapping completed.
See MAP report file "toplevel_gen_map.mrp" for details.
Problem encountered during the packing phase.

Design Summary
--------------
Number of errors   :   1
Number of warnings : 130

Process "Map" failed